Intel® 64 and IA-32 Architectures Software Developer’s Manual

Volume 2C: Instruction Set Reference, V-Z

NOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manual consists of ten volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-L, Order Number 253666; Instruction Set Reference M-U, Order Number 253667; Instruction Set Reference V-Z, Order Number 326018; Instruction Set Reference, Order Number 334569; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2, Order Number 253669; System Programming Guide, Part 3, Order Number 326019; System Programming Guide, Part 4, Order Number 332831; Model-Specific Registers, Order Number 335592. Refer to all ten volumes when evaluating your design needs.

Order Number: 326018-067US

May 2018

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CHAPTER 5 INSTRUCTION SET REFERENCE, V-Z

1. TERNARY BIT VECTOR LOGIC TABLE

   VPTERNLOGD/VPTERNLOGQ instructions operate on dword/qword elements and take three bit vectors of the respective input data elements to form a set of 32/64 indices, where each 3-bit value provides an index into an 8- bit lookup table represented by the imm8 byte of the instruction. The 256 possible values of the imm8 byte is constructed as a 16x16 boolean logic table. The 16 rows of the table uses the lower 4 bits of imm8 as row index. The 16 columns are referenced by imm8[7:4]. The 16 columns of the table are present in two halves, with 8 columns shown in Table 5-1 for the column index value between 0:7, followed by Table 5-2 showing the 8 columns corresponding to column index 8:15. This section presents the two-halves of the 256-entry table using a short- hand notation representing simple or compound boolean logic expressions with three input bit source data.

   The three input bit source data will be denoted with the capital letters: A, B, C; where A represents a bit from the first source operand (also the destination operand), B and C represent a bit from the 2nd and 3rd source operands.

   Each map entry takes the form of a logic expression consisting of one of more component expressions. Each component expression consists of either a unary or binary boolean operator and associated operands. Each binary boolean operator is expressed in lowercase letters, and operands concatenated after the logic operator. The unary operator ‘not’ is expressed using ‘!’. Additionally, the conditional expression “A?B:C” expresses a result returning B if A is set, returning C otherwise.

   A binary boolean operator is followed by two operands, e.g. andAB. For a compound binary expression that contain commutative components and comprising the same logic operator, the 2nd logic operator is omitted and three operands can be concatenated in sequence, e.g. andABC. When the 2nd operand of the first binary boolean expres- sion comes from the result of another boolean expression, the 2nd boolean expression is concatenated after the uppercase operand of the first logic expression, e.g. norBnandAC. When the result is independent of an operand, that operand is omitted in the logic expression, e.g. zeros or norCB.

   The 3-input expression “majorABC” returns 0 if two or more input bits are 0, returns 1 if two or more input bits are

   1. The 3-input expression “minorABC” returns 1 if two or more input bits are 0, returns 0 if two or more input bits are 1.

   The building-block bit logic functions used in Table 5-1 and Table 5-2 include;

   • Constants: TRUE (1), FALSE (0);

   • Unary function: Not (!);

   • Binary functions: and, nand, or, nor, xor, xnor;

   • Conditional function: Select (?:);

   • Tertiary functions: major, minor.

     
     

     : Table 5-1. Low 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations

     Imm	[7:4]
     [3:0]	0H	1H	2H	3H	4H	5H	6H	7H
     00H	FALSE	andAnorBC	norBnandAC	andA!B	norCnandBA	andA!C	andAxorBC	andAnandBC
     01H	norABC	norCB	norBxorAC	A?!B:norBC	norCxorBA	A?!C:norBC	A?xorBC:norB C	A?nandBC:no rBC
     02H	andCnorBA	norBxnorAC	andC!B	norBnorAC	C?norBA:and BA	C?norBA:A	C?!B:andBA	C?!B:A
     03H	norBA	norBandAC	C?!B:norBA	!B	C?norBA:xnor BA	A?!C:!B	A?xorBC:!B	A?nandBC:!B
     04H	andBnorAC	norCxnorBA	B?norAC:and AC	B?norAC:A	andB!C	norCnorBA	B?!C:andAC	B?!C:A
     05H	norCA	norCandBA	B?norAC:xnor AC	A?!B:!C	B?!C:norAC	!C	A?xorBC:!C	A?nandBC:!C
     06H	norAxnorBC	A?norBC:xorB C	B?norAC:C	xorBorAC	C?norBA:B	xorCorBA	xorCB	B?!C:orAC
     07H	norAandBC	minorABC	C?!B:!A	nandBorAC	B?!C:!A	nandCorBA	A?xorBC:nan dBC	nandCB
     08H	norAnandBC	A?norBC:and BC	andCxorBA	A?!B:andBC	andBxorAC	A?!C:andBC	A?xorBC:and BC	xorAandBC
     09H	norAxorBC	A?norBC:xnor BC	C?xorBA:norB A	A?!B:xnorBC	B?xorAC:norA C	A?!C:xnorBC	xnorABC	A?nandBC:xn orBC
     0AH	andC!A	A?norBC:C	andCnandBA	A?!B:C	C?!A:andBA	xorCA	xorCandBA	A?nandBC:C
     0BH	C?!A:norBA	C?!A:!B	C?nandBA:no rBA	C?nandBA:!B	B?xorAC:!A	B?xorAC:nan dAC	C?nandBA:xn orBA	nandBxnorAC
     0CH	andB!A	A?norBC:B	B?!A:andAC	xorBA	andBnandAC	A?!C:B	xorBandAC	A?nandBC:B
     0DH	B?!A:norAC	B?!A:!C	B?!A:xnorAC	C?xorBA:nan dBA	B?nandAC:no rAC	B?nandAC:!C	B?nandAC:xn orAC	nandCxnorBA
     0EH	norAnorBC	xorAorBC	B?!A:C	A?!B:orBC	C?!A:B	A?!C:orBC	B?nandAC:C	A?nandBC:or BC
     0FH	!A	nandAorBC	C?nandBA:!A	nandBA	B?nandAC:!A	nandCA	nandAxnorBC	nandABC

     
     

     Table 5-2 shows the half of 256-entry map corresponding to column index values 8:15.

     
     

     : Table 5-2. Low 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations

     Imm	[7:4]
     [3:0]	08H	09H	0AH	0BH	0CH	0DH	0EH	0FH
     00H	andABC	andAxnorBC	andCA	B?andAC:A	andBA	C?andBA:A	andAorBC	A
     01H	A?andBC:nor BC	B?andAC:!C	A?C:norBC	C?A:!B	A?B:norBC	B?A:!C	xnorAorBC	orAnorBC
     02H	andCxnorBA	B?andAC:xor AC	B?andAC:C	B?andAC:orA C	C?xnorBA:an dBA	B?A:xorAC	B?A:C	B?A:orAC
     03H	A?andBC:!B	xnorBandAC	A?C:!B	nandBnandA C	xnorBA	B?A:nandAC	A?orBC:!B	orA!B
     04H	andBxnorAC	C?andBA:xor BA	B?xnorAC:an dAC	B?xnorAC:A	C?andBA:B	C?andBA:orB A	C?A:B	C?A:orBA
     05H	A?andBC:!C	xnorCandBA	xnorCA	C?A:nandBA	A?B:!C	nandCnandB A	A?orBC:!C	orA!C
     06H	A?andBC:xor BC	xorABC	A?C:xorBC	B?xnorAC:orA C	A?B:xorBC	C?xnorBA:orB A	A?orBC:xorBC	orAxorBC
     07H	xnorAandBC	A?xnorBC:na ndBC	A?C:nandBC	nandBxorAC	A?B:nandBC	nandCxorBA	A?orBCnandB C	orAnandBC
     08H	andCB	A?xnorBC:an dBC	andCorAB	B?C:A	andBorAC	C?B:A	majorABC	orAandBC
     09H	B?C:norAC	xnorCB	xnorCorBA	C?orBA:!B	xnorBorAC	B?orAC:!C	A?orBC:xnorB C	orAxnorBC
     0AH	A?andBC:C	A?xnorBC:C	C	B?C:orAC	A?B:C	B?orAC:xorAC	orCandBA	orCA
     0BH	B?C:!A	B?C:nandAC	orCnorBA	orC!B	B?orAC:!A	B?orAC:nand AC	orCxnorBA	nandBnorAC
     0CH	A?andBC:B	A?xnorBC:B	A?C:B	C?orBA:xorBA	B	C?B:orBA	orBandAC	orBA
     0DH	C?B!A	C?B:nandBA	C?orBA:!A	C?orBA:nand BA	orBnorAC	orB!C	orBxnorAC	nandCnorBA
     0EH	A?andBC:orB C	A?xnorBC:orB C	A?C:orBC	orCxorBA	A?B:orBC	orBxorAC	orCB	orABC
     0FH	nandAnandB C	nandAxorBC	orC!A	orCnandBA	orB!A	orBnandAC	nandAnorBC	TRUE

     
     

     Table 5-1 and Table 5-2 translate each of the possible value of the imm8 byte to a Boolean expression. These tables can also be used by software to translate Boolean expressions to numerical constants to form the imm8 value needed to construct the VPTERNLOG syntax. There is a unique set of three byte constants (F0H, CCH, AAH) that can be used for this purpose as input operands in conjunction with the Boolean expressions defined in those tables. The reverse mapping can be expressed as:

     Result_imm8 = Table_Lookup_Entry( 0F0H, 0CCH, 0AAH)

     Table_Lookup_Entry is the Boolean expression defined in Table 5-1 and Table 5-2.

     
     

2. INSTRUCTIONS (V-Z)

Chapter 5 continues an alphabetical discussion of Intel® 64 and IA-32 instructions (V-Z). See also: Chapter 3, “Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Chapter 4, “Instruction Set Reference, M-U‚” in the Intel® 64 and IA-32 Architectures Software Devel- oper’s Manual, Volume 2B.

VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors

Instruction Operand Encoding

Description

Concatenates and shifts right doubleword/quadword elements of the first source operand (the second operand) and the second source operand (the third operand) into a 1024/512/256-bit intermediate vector. The low 512/256/128-bit of the intermediate vector is written to the destination operand (the first operand) using the writemask k1. The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location.

This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1 are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous values (merging-masking) or are set to 0 (zeroing-masking).

Operation

VALIGND (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF (SRC2 *is memory*) (AND EVEX.b = 1) THEN

FOR j  0 TO KL-1

i j * 32

src[i+31:i]  SRC2[31:0] ENDFOR;

ELSE src  SRC2

FI

; Concatenate sources tmp[VL-1:0]  src[VL-1:0]

tmp[2VL-1:VL]  SRC1[VL-1:0]

; Shift right doubleword elements IF VL = 128

THEN SHIFT = imm8[1:0] ELSE

IF VL = 256

THEN SHIFT = imm8[2:0] ELSE SHIFT = imm8[3:0]

FI

FI;

tmp[2VL-1:0]  tmp[2VL-1:0] >> (32*SHIFT)

; Apply writemask FOR j  0 TO KL-1

i j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i]  tmp[i+31:i] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR;

DEST[MAXVL-1:VL]  0

VALIGNQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256),(8, 512)

IF (SRC2 *is memory*) (AND EVEX.b = 1) THEN

FOR j  0 TO KL-1

i j * 64

src[i+63:i]  SRC2[63:0] ENDFOR;

ELSE src  SRC2

FI

; Concatenate sources tmp[VL-1:0]  src[VL-1:0]

tmp[2VL-1:VL]  SRC1[VL-1:0]

; Shift right quadword elements IF VL = 128

THEN SHIFT = imm8[0] ELSE

IF VL = 256

THEN SHIFT = imm8[1:0] ELSE SHIFT = imm8[2:0]

FI

FI;

tmp[2VL-1:0]  tmp[2VL-1:0] >> (64*SHIFT)

; Apply writemask FOR j  0 TO KL-1

i j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i]  tmp[i+63:i] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR;

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VALIGND m512i _mm512_alignr_epi32( m512i a, m512i b, int cnt);

VALIGND m512i _mm512_mask_alignr_epi32( m512i s, mmask16 k, m512i a, m512i b, int cnt); VALIGND m512i _mm512_maskz_alignr_epi32( mmask16 k, m512i a, m512i b, int cnt);

VALIGND m256i _mm256_mask_alignr_epi32( m256i s, mmask8 k, m256i a, m256i b, int cnt); VALIGND m256i _mm256_maskz_alignr_epi32( mmask8 k, m256i a, m256i b, int cnt);

VALIGND m128i _mm_mask_alignr_epi32( m128i s, mmask8 k, m128i a, m128i b, int cnt); VALIGND m128i _mm_maskz_alignr_epi32( mmask8 k, m128i a, m128i b, int cnt);

VALIGNQ m512i _mm512_alignr_epi64( m512i a, m512i b, int cnt);

VALIGNQ m512i _mm512_mask_alignr_epi64( m512i s, mmask8 k, m512i a, m512i b, int cnt); VALIGNQ m512i _mm512_maskz_alignr_epi64( mmask8 k, m512i a, m512i b, int cnt);

VALIGNQ m256i _mm256_mask_alignr_epi64( m256i s, mmask8 k, m256i a, m256i b, int cnt); VALIGNQ m256i _mm256_maskz_alignr_epi64( mmask8 k, m256i a, m256i b, int cnt);

VALIGNQ m128i _mm_mask_alignr_epi64( m128i s, mmask8 k, m128i a, m128i b, int cnt); VALIGNQ m128i _mm_maskz_alignr_epi64( mmask8 k, m128i a, m128i b, int cnt);

Exceptions

See Exceptions Type E4NF.

VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control

Instruction Operand Encoding

Description

Performs an element-by-element blending between float64/float32 elements in the first source operand (the second operand) with the elements in the second source operand (the third operand) using an opmask register as select control. The blended result is written to the destination register.

The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64- bit memory location.

The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every element of the destination is conditionally selected between first source or second source using the value of the related mask bit (0 for first source operand, 1 for second source operand).

If EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.

Operation

VBLENDMPD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no controlmask* THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN

DEST[i+63:i]  SRC2[63:0] ELSE

DEST[i+63:i]  SRC2[i+63:i]

FI;

ELSE

IF *merging-masking* ; merging-masking THEN DEST[i+63:i]  SRC1[i+63:i]

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI;

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VBLENDMPS (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j  0 TO KL-1

i  j * 32

IF k1[j] OR *no controlmask* THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN

DEST[i+31:i]  SRC2[31:0] ELSE

DEST[i+31:i]  SRC2[i+31:i]

FI;

ELSE

IF *merging-masking* ; merging-masking THEN DEST[i+31:i]  SRC1[i+31:i]

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI;

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VBLENDMPD m512d _mm512_mask_blend_pd( mmask8 k, m512d a, m512d b); VBLENDMPD m256d _mm256_mask_blend_pd( mmask8 k, m256d a, m256d b); VBLENDMPD m128d _mm_mask_blend_pd( mmask8 k, m128d a, m128d b); VBLENDMPS m512 _mm512_mask_blend_ps( mmask16 k, m512 a, m512 b); VBLENDMPS m256 _mm256_mask_blend_ps( mmask8 k, m256 a, m256 b); VBLENDMPS m128 _mm_mask_blend_ps( mmask8 k, m128 a, m128 b);

SIMD Floating-Point Exceptions

None

Other Exceptions

See Exceptions Type E4.

VBROADCAST—Load with Broadcast Floating-Point Data

Instruction Operand Encoding

Description

VBROADCASTSD/VBROADCASTSS/VBROADCASTF128 load floating-point values as one tuple from the source operand (second operand) in memory and broadcast to all elements of the destination operand (first operand).

VEX256-encoded versions: The destination operand is a YMM register. The source operand is either a 32-bit, 64- bit, or 128-bit memory location. Register source encodings are reserved and will #UD. Bits (MAXVL-1:256) of the destination register are zeroed.

EVEX-encoded versions: The destination operand is a ZMM/YMM/XMM register and updated according to the writemask k1. The source operand is either a 32-bit, 64-bit memory location or the low doubleword/quadword element of an XMM register.

VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2/VBROADCASTF32X8/VBROADCASTF64X4 load

floating-point values as tuples from the source operand (the second operand) in memory or register and broadcast to all elements of the destination operand (the first operand). The destination operand is a YMM/ZMM register updated according to the writemask k1. The source operand is either a register or 64-bit/128-bit/256-bit memory location.

VBROADCASTSD and VBROADCASTF128,F32x4 and F64x2 are only supported as 256-bit and 512-bit wide versions and up. VBROADCASTSS is supported in 128-bit, 256-bit and 512-bit wide versions. F32x8 and F64x4 are only supported as 512-bit wide versions.

VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF32X8 have 32-bit granularity. VBROADCASTF64X2 and

VBROADCASTF64X4 have 64-bit granularity.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

If VBROADCASTSD or VBROADCASTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an #UD exception.

X0

m32

DEST

Figure 5-1. VBROADCASTSS Operation (VEX.256 encoded version)

X0

m32

DEST

Figure 5-2. VBROADCASTSS Operation (VEX.128-bit version)

X0

m64

DEST

Figure 5-3. VBROADCASTSD Operation (VEX.256-bit version)

m128

X0

DEST

X0

X0

Figure 5-4. VBROADCASTF128 Operation (VEX.256-bit version)

m256

X0

DEST

X0

X0

Figure 5-5. VBROADCASTF64X4 Operation (512-bit version with writemask all 1s)

Operation

VBROADCASTSS (128 bit version VEX and legacy)

temp  SRC[31:0] DEST[31:0]  temp DEST[63:32]  temp DEST[95:64]  temp DEST[127:96]  temp DEST[MAXVL-1:128]  0

VBROADCASTSS (VEX.256 encoded version)

temp  SRC[31:0] DEST[31:0]  temp DEST[63:32]  temp DEST[95:64]  temp DEST[127:96]  temp DEST[159:128]  temp DEST[191:160]  temp DEST[223:192]  temp DEST[255:224]  temp DEST[MAXVL-1:256]  0

VBROADCASTSS (EVEX encoded versions)

(KL, VL) (4, 128), (8, 256),= (16, 512)

FOR j  0 TO KL-1

i j * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i]  SRC[31:0] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VBROADCASTSD (VEX.256 encoded version)

temp  SRC[63:0] DEST[63:0]  temp DEST[127:64]  temp DEST[191:128]  temp DEST[255:192]  temp DEST[MAXVL-1:256]  0

VBROADCASTSD (EVEX encoded versions)

(KL, VL) = (4, 256), (8, 512)

FOR j  0 TO KL-1

i j * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i]  SRC[63:0] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VBROADCASTF32x2 (EVEX encoded versions)

(KL, VL) = (8, 256), (16, 512)

FOR j  0 TO KL-1

i  j * 32

n  (j mod 2) * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i]  SRC[n+31:n] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VBROADCASTF128 (VEX.256 encoded version)

temp  SRC[127:0] DEST[127:0]  temp DEST[255:128]  temp DEST[MAXVL-1:256]  0

VBROADCASTF32X4 (EVEX encoded versions)

(KL, VL) = (8, 256), (16, 512)

FOR j  0 TO KL-1

i  j* 32

n  (j modulo 4) * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i]  SRC[n+31:n] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VBROADCASTF64X2 (EVEX encoded versions)

(KL, VL) = (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

n (j modulo 2) * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i]  SRC[n+63:n] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i] = 0

FI

FI;

ENDFOR;

VBROADCASTF32X8 (EVEX.U1.512 encoded version)

FOR j  0 TO 15

i  j * 32

n (j modulo 8) * 32

IF k1[j] OR *no writemask*

THEN DEST[i+31:i]  SRC[n+31:n] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VBROADCASTF64X4 (EVEX.512 encoded version)

FOR j  0 TO 7

i  j * 64

n  (j modulo 4) * 64

IF k1[j] OR *no writemask*

THEN DEST[i+63:i]  SRC[n+63:n] ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VBROADCASTF32x2 m512 _mm512_broadcast_f32x2( m128 a);

VBROADCASTF32x2 m512 _mm512_mask_broadcast_f32x2( m512 s, mmask16 k, m128 a); VBROADCASTF32x2 m512 _mm512_maskz_broadcast_f32x2( mmask16 k, m128 a); VBROADCASTF32x2 m256 _mm256_broadcast_f32x2( m128 a);

VBROADCASTF32x2 m256 _mm256_mask_broadcast_f32x2( m256 s, mmask8 k, m128 a); VBROADCASTF32x2 m256 _mm256_maskz_broadcast_f32x2( mmask8 k, m128 a); VBROADCASTF32x4 m512 _mm512_broadcast_f32x4( m128 a);

VBROADCASTF32x4 m512 _mm512_mask_broadcast_f32x4( m512 s, mmask16 k, m128 a); VBROADCASTF32x4 m512 _mm512_maskz_broadcast_f32x4( mmask16 k, m128 a); VBROADCASTF32x4 m256 _mm256_broadcast_f32x4( m128 a);

VBROADCASTF32x4 m256 _mm256_mask_broadcast_f32x4( m256 s, mmask8 k, m128 a); VBROADCASTF32x4 m256 _mm256_maskz_broadcast_f32x4( mmask8 k, m128 a); VBROADCASTF32x8 m512 _mm512_broadcast_f32x8( m256 a);

VBROADCASTF32x8 m512 _mm512_mask_broadcast_f32x8( m512 s, mmask16 k, m256 a); VBROADCASTF32x8 m512 _mm512_maskz_broadcast_f32x8( mmask16 k, m256 a); VBROADCASTF64x2 m512d _mm512_broadcast_f64x2( m128d a);

VBROADCASTF64x2 m512d _mm512_mask_broadcast_f64x2( m512d s, mmask8 k, m128d a); VBROADCASTF64x2 m512d _mm512_maskz_broadcast_f64x2( mmask8 k, m128d a); VBROADCASTF64x2 m256d _mm256_broadcast_f64x2( m128d a);

VBROADCASTF64x2 m256d _mm256_mask_broadcast_f64x2( m256d s, mmask8 k, m128d a); VBROADCASTF64x2 m256d _mm256_maskz_broadcast_f64x2( mmask8 k, m128d a); VBROADCASTF64x4 m512d _mm512_broadcast_f64x4( m256d a);

VBROADCASTF64x4 m512d _mm512_mask_broadcast_f64x4( m512d s, mmask8 k, m256d a); VBROADCASTF64x4 m512d _mm512_maskz_broadcast_f64x4( mmask8 k, m256d a); VBROADCASTSD m512d _mm512_broadcastsd_pd( m128d a);

VBROADCASTSD m512d _mm512_mask_broadcastsd_pd( m512d s, mmask8 k, m128d a); VBROADCASTSD m512d _mm512_maskz_broadcastsd_pd( mmask8 k, m128d a); VBROADCASTSD m256d _mm256_broadcastsd_pd( m128d a);

VBROADCASTSD m256d _mm256_mask_broadcastsd_pd( m256d s, mmask8 k, m128d a); VBROADCASTSD m256d _mm256_maskz_broadcastsd_pd( mmask8 k, m128d a); VBROADCASTSD m256d _mm256_broadcast_sd(double *a);

VBROADCASTSS m512 _mm512_broadcastss_ps( m128 a);

VBROADCASTSS m512 _mm512_mask_broadcastss_ps( m512 s, mmask16 k, m128 a); VBROADCASTSS m512 _mm512_maskz_broadcastss_ps( mmask16 k, m128 a); VBROADCASTSS m256 _mm256_broadcastss_ps( m128 a);

VBROADCASTSS m256 _mm256_mask_broadcastss_ps( m256 s, mmask8 k, m128 a); VBROADCASTSS m256 _mm256_maskz_broadcastss_ps( mmask8 k, m128 a);

VBROADCASTSS m128 _mm_broadcastss_ps( m128 a);

VBROADCASTSS m128 _mm_mask_broadcastss_ps( m128 s, mmask8 k, m128 a); VBROADCASTSS m128 _mm_maskz_broadcastss_ps( mmask8 k, m128 a); VBROADCASTSS m128 _mm_broadcast_ss(float *a);

VBROADCASTSS m256 _mm256_broadcast_ss(float *a); VBROADCASTF128 m256 _mm256_broadcast_ps( m128 * a); VBROADCASTF128 m256d _mm256_broadcast_pd( m128d * a);

Exceptions

VEX-encoded instructions, see Exceptions Type 6; EVEX-encoded instructions, see Exceptions Type E6.

#UD If VEX.L = 0 for VBROADCASTSD or VBROADCASTF128.

If EVEX.L’L = 0 for VBROADCASTSD/VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2. If EVEX.L’L < 10b for VBROADCASTF32X8/VBROADCASTF64X4.

VCOMPRESSPD—Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory

Instruction Operand Encoding

Description

Compress (store) up to 8 double-precision floating-point values from the source operand (the second operand) as a contiguous vector to the destination operand (the first operand) The source operand is a ZMM/YMM/XMM register, the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.

The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the destination starting from the low element of the destination operand.

Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z must be zero.

Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper bits are zeroed.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.

Operation

VCOMPRESSPD (EVEX encoded versions) store form

(KL, VL) = (2, 128), (4, 256), (8, 512)

SIZE  64

k  0

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN

DEST[k+SIZE-1:k] SRC[i+63:i]

k  k + SIZE

FI;

ENDFOR

VCOMPRESSPD (EVEX encoded versions) reg-reg form

(KL, VL) = (2, 128), (4, 256), (8, 512)

SIZE  64

k  0

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN

DEST[k+SIZE-1:k] SRC[i+63:i]

k  k + SIZE

FI;

ENDFOR

IF *merging-masking*

THEN *DEST[VL-1:k] remains unchanged*

ELSE DEST[VL-1:k]  0

FI

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCOMPRESSPD m512d _mm512_mask_compress_pd( m512d s, mmask8 k, m512d a); VCOMPRESSPD m512d _mm512_maskz_compress_pd( mmask8 k, m512d a); VCOMPRESSPD void _mm512_mask_compressstoreu_pd( void * d, mmask8 k, m512d a); VCOMPRESSPD m256d _mm256_mask_compress_pd( m256d s, mmask8 k, m256d a); VCOMPRESSPD m256d _mm256_maskz_compress_pd( mmask8 k, m256d a); VCOMPRESSPD void _mm256_mask_compressstoreu_pd( void * d, mmask8 k, m256d a); VCOMPRESSPD m128d _mm_mask_compress_pd( m128d s, mmask8 k, m128d a); VCOMPRESSPD m128d _mm_maskz_compress_pd( mmask8 k, m128d a); VCOMPRESSPD void _mm_mask_compressstoreu_pd( void * d, mmask8 k, m128d a);

SIMD Floating-Point Exceptions

None

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E4.nb.

#UD If EVEX.vvvv != 1111B.

VCOMPRESSPS—Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory

Instruction Operand Encoding

Description

Compress (stores) up to 16 single-precision floating-point values from the source operand (the second operand) to the destination operand (the first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.

The opmask register k1 selects the active elements (a partial vector or possibly non-contiguous if less than 16 active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the destination starting from the low element of the destination operand.

Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z must be zero.

Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper bits are zeroed.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.

Operation

VCOMPRESSPS (EVEX encoded versions) store form

(KL, VL) = (4, 128), (8, 256), (16, 512)

SIZE  32

k  0

FOR j  0 TO KL-1

i  j * 32

IF k1[j] OR *no writemask* THEN

DEST[k+SIZE-1:k] SRC[i+31:i]

k  k + SIZE

FI;

ENDFOR;

VCOMPRESSPS (EVEX encoded versions) reg-reg form

(KL, VL) = (4, 128), (8, 256), (16, 512)

SIZE  32

k  0

FOR j  0 TO KL-1

i  j * 32

IF k1[j] OR *no writemask* THEN

DEST[k+SIZE-1:k] SRC[i+31:i]

k  k + SIZE

FI;

ENDFOR

IF *merging-masking*

THEN *DEST[VL-1:k] remains unchanged* ELSE DEST[VL-1:k]  0

FI

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCOMPRESSPS m512 _mm512_mask_compress_ps( m512 s, mmask16 k, m512 a); VCOMPRESSPS m512 _mm512_maskz_compress_ps( mmask16 k, m512 a); VCOMPRESSPS void _mm512_mask_compressstoreu_ps( void * d, mmask16 k, m512 a); VCOMPRESSPS m256 _mm256_mask_compress_ps( m256 s, mmask8 k, m256 a); VCOMPRESSPS m256 _mm256_maskz_compress_ps( mmask8 k, m256 a); VCOMPRESSPS void _mm256_mask_compressstoreu_ps( void * d, mmask8 k, m256 a); VCOMPRESSPS m128 _mm_mask_compress_ps( m128 s, mmask8 k, m128 a); VCOMPRESSPS m128 _mm_maskz_compress_ps( mmask8 k, m128 a); VCOMPRESSPS void _mm_mask_compressstoreu_ps( void * d, mmask8 k, m128 a);

SIMD Floating-Point Exceptions

None

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E4.nb.

#UD If EVEX.vvvv != 1111B.

VCVTPD2QQ—Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers

Instruction Operand Encoding

Description

Converts packed double-precision floating-point values in the source operand (second operand) to packed quad- word integers in the destination operand (first operand).

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTPD2QQ (EVEX encoded version) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL == 512) AND (EVEX.b == 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTPD2QQ (EVEX encoded version) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b == 1) THEN

DEST[i+63:i]  Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[63:0]) ELSE

DEST[i+63:i]  Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])

FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPD2QQ m512i _mm512_cvtpd_epi64( m512d a);

VCVTPD2QQ m512i _mm512_mask_cvtpd_epi64( m512i s, mmask8 k, m512d a); VCVTPD2QQ m512i _mm512_maskz_cvtpd_epi64( mmask8 k, m512d a); VCVTPD2QQ m512i _mm512_cvt_roundpd_epi64( m512d a, int r);

VCVTPD2QQ m512i _mm512_mask_cvt_roundpd_epi64( m512i s, mmask8 k, m512d a, int r); VCVTPD2QQ m512i _mm512_maskz_cvt_roundpd_epi64( mmask8 k, m512d a, int r); VCVTPD2QQ m256i _mm256_mask_cvtpd_epi64( m256i s, mmask8 k, m256d a); VCVTPD2QQ m256i _mm256_maskz_cvtpd_epi64( mmask8 k, m256d a);

VCVTPD2QQ m128i _mm_mask_cvtpd_epi64( m128i s, mmask8 k, m128d a); VCVTPD2QQ m128i _mm_maskz_cvtpd_epi64( mmask8 k, m128d a); VCVTPD2QQ m256i _mm256_cvtpd_epi64 ( m256d src)

VCVTPD2QQ m128i _mm_cvtpd_epi64 ( m128d src)

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2

#UD If EVEX.vvvv != 1111B.

VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers

Instruction Operand Encoding

Description

Converts packed double-precision floating-point values in the source operand (the second operand) to packed unsigned doubleword integers in the destination operand (the first operand).

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are zeroed.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTPD2UDQ (EVEX encoded versions) when src2 operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j  0 TO KL-1

i  j * 32 k  j * 64

IF k1[j] OR *no writemask* THEN

DEST[i+31:i] 

Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2]  0

VCVTPD2UDQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 32 k  j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) THEN

DEST[i+31:i] 

Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]) ELSE

DEST[i+31:i] 

Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPD2UDQ m256i _mm512_cvtpd_epu32( m512d a);

VCVTPD2UDQ m256i _mm512_mask_cvtpd_epu32( m256i s, mmask8 k, m512d a); VCVTPD2UDQ m256i _mm512_maskz_cvtpd_epu32( mmask8 k, m512d a); VCVTPD2UDQ m256i _mm512_cvt_roundpd_epu32( m512d a, int r);

VCVTPD2UDQ m256i _mm512_mask_cvt_roundpd_epu32( m256i s, mmask8 k, m512d a, int r); VCVTPD2UDQ m256i _mm512_maskz_cvt_roundpd_epu32( mmask8 k, m512d a, int r); VCVTPD2UDQ m128i _mm256_mask_cvtpd_epu32( m128i s, mmask8 k, m256d a); VCVTPD2UDQ m128i _mm256_maskz_cvtpd_epu32( mmask8 k, m256d a);

VCVTPD2UDQ m128i _mm_mask_cvtpd_epu32( m128i s, mmask8 k, m128d a); VCVTPD2UDQ m128i _mm_maskz_cvtpd_epu32( mmask8 k, m128d a);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.

#UD If EVEX.vvvv != 1111B.

VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers

Instruction Operand Encoding

Description

Converts packed double-precision floating-point values in the source operand (second operand) to packed unsigned quadword integers in the destination operand (first operand).

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTPD2UQQ (EVEX encoded versions) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL == 512) AND (EVEX.b == 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTPD2UQQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b == 1) THEN

DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[63:0]) ELSE

DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTPD2UQQ m512i _mm512_cvtpd_epu64( m512d a);

VCVTPD2UQQ m512i _mm512_mask_cvtpd_epu64( m512i s, mmask8 k, m512d a); VCVTPD2UQQ m512i _mm512_maskz_cvtpd_epu64( mmask8 k, m512d a); VCVTPD2UQQ m512i _mm512_cvt_roundpd_epu64( m512d a, int r);

VCVTPD2UQQ m512i _mm512_mask_cvt_roundpd_epu64( m512i s, mmask8 k, m512d a, int r); VCVTPD2UQQ m512i _mm512_maskz_cvt_roundpd_epu64( mmask8 k, m512d a, int r); VCVTPD2UQQ m256i _mm256_mask_cvtpd_epu64( m256i s, mmask8 k, m256d a); VCVTPD2UQQ m256i _mm256_maskz_cvtpd_epu64( mmask8 k, m256d a);

VCVTPD2UQQ m128i _mm_mask_cvtpd_epu64( m128i s, mmask8 k, m128d a); VCVTPD2UQQ m128i _mm_maskz_cvtpd_epu64( mmask8 k, m128d a); VCVTPD2UQQ m256i _mm256_cvtpd_epu64 ( m256d src)

VCVTPD2UQQ m128i _mm_cvtpd_epu64 ( m128d src)

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2

#UD If EVEX.vvvv != 1111B.

VCVTPH2PS—Convert 16-bit FP values to Single-Precision FP values

Instruction Operand Encoding

Description

Converts packed half precision (16-bits) floating-point values in the low-order bits of the source operand (the second operand) to packed single-precision floating-point values and writes the converted values into the destina- tion operand (the first operand).

If case of a denormal operand, the correct normal result is returned. MXCSR.DAZ is ignored and is treated as if it

1. No denormal exception is reported on MXCSR.

   VEX.128 version: The source operand is a XMM register or 64-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding destination register are zeroed.

   VEX.256 version: The source operand is a XMM register or 128-bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.

   EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

   The diagram below illustrates how data is converted from four packed half precision (in 64 bits) to four single preci- sion (in 128 bits) FP values.

   Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).

   
   

   
   

   VCVTPH2PS xmm1, xmm2/mem64, imm8

   
   

   127

   96 95

   64 63

   48 47

   32 31

   16 15

   0

   
   

   VH3 VH2 VH1 VH0 xmm2/mem64

   
   

   convert

   convert

   
   

   convert

   convert

   
   

   127

   96 95

   64 63

   32 31

   0

   
   

   VS3 VS2 VS1 VS0 xmm1

   
   

   

   Figure 5-6. VCVTPH2PS (128-bit Version)

   
   

   
   

   Operation

   vCvt_h2s(SRC1[15:0])

   {

   RETURN Cvt_Half_Precision_To_Single_Precision(SRC1[15:0]);

   }

   
   

   VCVTPH2PS (EVEX encoded versions)

   (KL, VL) = (4, 128), (8, 256), (16, 512)

   FOR j  0 TO KL-1

   i  j * 32 k  j * 16

   IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

   vCvt_h2s(SRC[k+15:k]) ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+31:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   VCVTPH2PS (VEX.256 encoded version) DEST[31:0] vCvt_h2s(SRC1[15:0]); DEST[63:32] vCvt_h2s(SRC1[31:16]); DEST[95:64] vCvt_h2s(SRC1[47:32]); DEST[127:96] vCvt_h2s(SRC1[63:48]); DEST[159:128] vCvt_h2s(SRC1[79:64]); DEST[191:160] vCvt_h2s(SRC1[95:80]); DEST[223:192] vCvt_h2s(SRC1[111:96]);

   DEST[255:224] vCvt_h2s(SRC1[127:112]);

   DEST[MAXVL-1:256]  0

   
   

   
   

   VCVTPH2PS (VEX.128 encoded version) DEST[31:0] vCvt_h2s(SRC1[15:0]); DEST[63:32] vCvt_h2s(SRC1[31:16]); DEST[95:64] vCvt_h2s(SRC1[47:32]); DEST[127:96] vCvt_h2s(SRC1[63:48]); DEST[MAXVL-1:128]  0

   
   

   Flags Affected

   None

   
   

   Intel C/C++ Compiler Intrinsic Equivalent

   VCVTPH2PS m512 _mm512_cvtph_ps( m256i a);

   VCVTPH2PS m512 _mm512_mask_cvtph_ps( m512 s, mmask16 k, m256i a); VCVTPH2PS m512 _mm512_maskz_cvtph_ps( mmask16 k, m256i a); VCVTPH2PS m512 _mm512_cvt_roundph_ps( m256i a, int sae);

   VCVTPH2PS m512 _mm512_mask_cvt_roundph_ps( m512 s, mmask16 k, m256i a, int sae); VCVTPH2PS m512 _mm512_maskz_cvt_roundph_ps( mmask16 k, m256i a, int sae); VCVTPH2PS m256 _mm256_mask_cvtph_ps( m256 s, mmask8 k, m128i a);

   VCVTPH2PS m256 _mm256_maskz_cvtph_ps( mmask8 k, m128i a); VCVTPH2PS m128 _mm_mask_cvtph_ps( m128 s, mmask8 k, m128i a); VCVTPH2PS m128 _mm_maskz_cvtph_ps( mmask8 k, m128i a); VCVTPH2PS m128 _mm_cvtph_ps ( m128i m1);

   VCVTPH2PS m256 _mm256_cvtph_ps ( m128i m1)

   
   

   SIMD Floating-Point Exceptions

   Invalid

   
   

   Other Exceptions

   VEX-encoded instructions, see Exceptions Type 11 (do not report #AC); EVEX-encoded instructions, see Exceptions Type E11.

   #UD If VEX.W=1.

   #UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

   
   

   VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value

   Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
   VEX.128.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m64, xmm2, imm8	A	V/V	F16C	Convert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls.
   VEX.256.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m128, ymm2, imm8	A	V/V	F16C	Convert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls.
   EVEX.128.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m64 {k1}{z}, xmm2, imm8	B	V/V	AVX512VL AVX512F	Convert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls.
   EVEX.256.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m128 {k1}{z}, ymm2, imm8	B	V/V	AVX512VL AVX512F	Convert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls.
   EVEX.512.66.0F3A.W0 1D /r ib VCVTPS2PH ymm1/m256 {k1}{z}, zmm2{sae}, imm8	B	V/V	AVX512F	Convert sixteen packed single-precision floating-point values in zmm2 to packed half-precision (16-bit) floating- point values in ymm1/m256. Imm8 provides rounding controls.

   
   

   Instruction Operand Encoding

   Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
   A	NA	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA
   B	Half Mem	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA

   Description

   Convert packed single-precision floating values in the source operand to half-precision (16-bit) floating-point values and store to the destination operand. The rounding mode is specified using the immediate field (imm8).

   

   Underflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is denormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception will be raised with DE, UE and PE set.

   
   

   VCVTPS2PH xmm1/mem64, xmm2, imm8

   
   

   127

   96 95

   64 63

   32 31

   0

   
   

   VS3 VS2 VS1 VS0 xmm2

   
   

   convert

   convert

   convert

   convert

   
   

   127

   96 95

   64 63

   48 47

   32 31

   16 15

   0

   
   

   VH3 VH2 VH1 VH0 xmm1/mem64

   
   

   Figure 5-7. VCVTPS2PH (128-bit Version)

   
   

   
   

   The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC field are listed in Table 5-3.

   
   

   Table 5-3. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions

   Bits	Field Name/value	Description	Comment
   Imm[1:0]	RC=00B	Round to nearest even	If Imm[2] = 0
   	RC=01B	Round down
   	RC=10B	Round up
   	RC=11B	Truncate
   Imm[2]	MS1=0	Use imm[1:0] for rounding	Ignore MXCSR.RC
   	MS1=1	Use MXCSR.RC for rounding
   Imm[7:3]	Ignored	Ignored by processor

   VEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit memory location. If the destination operand is a register then the upper bits (MAXVL-1:64) of corresponding register are zeroed.

   VEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit memory location. If the destination operand is a register, the upper bits (MAXVL-1:128) of the corresponding desti- nation register are zeroed.

   Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).

   EVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask k1. Bits (MAXVL-1:256/128/64) of the corresponding destination register are zeroed.

   
   

   Operation

   vCvt_s2h(SRC1[31:0])

   {

   IF Imm[2] = 0

   THEN ; using Imm[1:0] for rounding control, see Table 5-3

   RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]); ELSE ; using MXCSR.RC for rounding control

   RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);

   FI;

   }

   
   

   VCVTPS2PH (EVEX encoded versions) when dest is a register

   (KL, VL) = (4, 128), (8, 256), (16, 512)

   FOR j  0 TO KL-1

   i  j * 16 k  j * 32

   IF k1[j] OR *no writemask* THEN DEST[i+15:i] 

   vCvt_s2h(SRC[k+31:k]) ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+15:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+15:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL/2]  0

   
   

   
   

   VCVTPS2PH (EVEX encoded versions) when dest is memory

   (KL, VL) = (4, 128), (8, 256), (16, 512)

   FOR j  0 TO KL-1

   i  j * 16 k  j * 32

   IF k1[j] OR *no writemask* THEN DEST[i+15:i] 

   vCvt_s2h(SRC[k+31:k]) ELSE

   *DEST[i+15:i] remains unchanged* ; merging-masking

   FI;

   ENDFOR

   
   

   VCVTPS2PH (VEX.256 encoded version) DEST[15:0] vCvt_s2h(SRC1[31:0]); DEST[31:16] vCvt_s2h(SRC1[63:32]); DEST[47:32] vCvt_s2h(SRC1[95:64]); DEST[63:48] vCvt_s2h(SRC1[127:96]); DEST[79:64] vCvt_s2h(SRC1[159:128]); DEST[95:80] vCvt_s2h(SRC1[191:160]); DEST[111:96] vCvt_s2h(SRC1[223:192]);

   DEST[127:112] vCvt_s2h(SRC1[255:224]);

   DEST[MAXVL-1:128]  0

   
   

   VCVTPS2PH (VEX.128 encoded version) DEST[15:0] vCvt_s2h(SRC1[31:0]); DEST[31:16] vCvt_s2h(SRC1[63:32]); DEST[47:32] vCvt_s2h(SRC1[95:64]); DEST[63:48] vCvt_s2h(SRC1[127:96]); DEST[MAXVL-1:64]  0

   
   

   Flags Affected

   None

   
   

   Intel C/C++ Compiler Intrinsic Equivalent

   VCVTPS2PH m256i _mm512_cvtps_ph( m512 a);

   VCVTPS2PH m256i _mm512_mask_cvtps_ph( m256i s, mmask16 k, m512 a); VCVTPS2PH m256i _mm512_maskz_cvtps_ph( mmask16 k, m512 a); VCVTPS2PH m256i _mm512_cvt_roundps_ph( m512 a, const int imm);

   VCVTPS2PH m256i _mm512_mask_cvt_roundps_ph( m256i s, mmask16 k, m512 a, const int imm); VCVTPS2PH m256i _mm512_maskz_cvt_roundps_ph( mmask16 k, m512 a, const int imm); VCVTPS2PH m128i _mm256_mask_cvtps_ph( m128i s, mmask8 k, m256 a);

   VCVTPS2PH m128i _mm256_maskz_cvtps_ph( mmask8 k, m256 a); VCVTPS2PH m128i _mm_mask_cvtps_ph( m128i s, mmask8 k, m128 a); VCVTPS2PH m128i _mm_maskz_cvtps_ph( mmask8 k, m128 a); VCVTPS2PH m128i _mm_cvtps_ph ( m128 m1, const int imm);

   VCVTPS2PH m128i _mm256_cvtps_ph( m256 m1, const int imm);

   
   

   SIMD Floating-Point Exceptions

   Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0);

   
   

   
   

   Other Exceptions

   VEX-encoded instructions, see Exceptions Type 11 (do not report #AC); EVEX-encoded instructions, see Exceptions Type E11.

   #UD If VEX.W=1.

   #UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

   
   

   VCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values

   Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
   EVEX.128.0F.W0 79 /r VCVTPS2UDQ xmm1 {k1}{z}, xmm2/m128/m32bcst	A	V/V	AVX512VL AVX512F	Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed unsigned doubleword values in xmm1 subject to writemask k1.
   EVEX.256.0F.W0 79 /r VCVTPS2UDQ ymm1 {k1}{z}, ymm2/m256/m32bcst	A	V/V	AVX512VL AVX512F	Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed unsigned doubleword values in ymm1 subject to writemask k1.
   EVEX.512.0F.W0 79 /r VCVTPS2UDQ zmm1 {k1}{z}, zmm2/m512/m32bcst{er}	A	V/V	AVX512F	Convert sixteen packed single-precision floating-point values from zmm2/m512/m32bcst to sixteen packed unsigned doubleword values in zmm1 subject to writemask k1.

   
   

   Instruction Operand Encoding

   Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
   A	Full	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

   Description

   Converts sixteen packed single-precision floating-point values in the source operand to sixteen unsigned double- word integers in the destination operand.

   When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

   The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

   Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

   
   

   
   

   Operation

   VCVTPS2UDQ (EVEX encoded versions) when src operand is a register

   (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

   THEN

   SET_RM(EVEX.RC);

   ELSE

   SET_RM(MXCSR.RM);

   FI;

   
   

   FOR j  0 TO KL-1

   i  j * 32

   IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

   Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i]) ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+31:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   VCVTPS2UDQ (EVEX encoded versions) when src operand is a memory source

   (KL, VL) = (4, 128), (8, 256), (16, 512)

   
   

   FOR j  0 TO KL-1

   i  j * 32

   IF k1[j] OR *no writemask* THEN

   IF (EVEX.b = 1) THEN

   DEST[i+31:i] 

   Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]) ELSE

   DEST[i+31:i] 

   Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i]) FI;

   ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+31:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   
   

   Intel C/C++ Compiler Intrinsic Equivalent

   VCVTPS2UDQ m512i _mm512_cvtps_epu32( m512 a);

   VCVTPS2UDQ m512i _mm512_mask_cvtps_epu32( m512i s, mmask16 k, m512 a); VCVTPS2UDQ m512i _mm512_maskz_cvtps_epu32( mmask16 k, m512 a); VCVTPS2UDQ m512i _mm512_cvt_roundps_epu32( m512 a, int r);

   VCVTPS2UDQ m512i _mm512_mask_cvt_roundps_epu32( m512i s, mmask16 k, m512 a, int r); VCVTPS2UDQ m512i _mm512_maskz_cvt_roundps_epu32( mmask16 k, m512 a, int r); VCVTPS2UDQ m256i _mm256_cvtps_epu32( m256d a);

   VCVTPS2UDQ m256i _mm256_mask_cvtps_epu32( m256i s, mmask8 k, m256 a); VCVTPS2UDQ m256i _mm256_maskz_cvtps_epu32( mmask8 k, m256 a); VCVTPS2UDQ m128i _mm_cvtps_epu32( m128 a);

   VCVTPS2UDQ m128i _mm_mask_cvtps_epu32( m128i s, mmask8 k, m128 a); VCVTPS2UDQ m128i _mm_maskz_cvtps_epu32( mmask8 k, m128 a);

   
   

   SIMD Floating-Point Exceptions

   Invalid, Precision

   
   

   Other Exceptions

   EVEX-encoded instructions, see Exceptions Type E2.

   #UD If EVEX.vvvv != 1111B.

   
   

   VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values

   Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
   EVEX.128.66.0F.W0 7B /r VCVTPS2QQ xmm1 {k1}{z}, xmm2/m64/m32bcst	A	V/V	AVX512VL AVX512DQ	Convert two packed single precision floating-point values from xmm2/m64/m32bcst to two packed signed quadword values in xmm1 subject to writemask k1.
   EVEX.256.66.0F.W0 7B /r VCVTPS2QQ ymm1 {k1}{z}, xmm2/m128/m32bcst	A	V/V	AVX512VL AVX512DQ	Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed quadword values in ymm1 subject to writemask k1.
   EVEX.512.66.0F.W0 7B /r VCVTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er}	A	V/V	AVX512DQ	Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 subject to writemask k1.

   
   

   Instruction Operand Encoding

   Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
   A	Half	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

   Description

   Converts eight packed single-precision floating-point values in the source operand to eight signed quadword inte- gers in the destination operand.

   When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.

   The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina- tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.

   Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

   
   

   
   

   Operation

   VCVTPS2QQ (EVEX encoded versions) when src operand is a register

   (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL == 512) AND (EVEX.b == 1)

   THEN

   SET_RM(EVEX.RC);

   ELSE

   SET_RM(MXCSR.RM);

   FI;

   FOR j  0 TO KL-1

   i  j * 64 k  j * 32

   IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

   Convert_Single_Precision_To_QuadInteger(SRC[k+31:k]) ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+63:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   VCVTPS2QQ (EVEX encoded versions) when src operand is a memory source

   (KL, VL) = (2, 128), (4, 256), (8, 512)

   
   

   FOR j  0 TO KL-1

   i  j * 64 k  j * 32

   IF k1[j] OR *no writemask* THEN

   IF (EVEX.b == 1) THEN

   DEST[i+63:i] 

   Convert_Single_Precision_To_QuadInteger(SRC[31:0]) ELSE

   DEST[i+63:i] 

   Convert_Single_Precision_To_QuadInteger(SRC[k+31:k]) FI;

   ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+63:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   
   

   Intel C/C++ Compiler Intrinsic Equivalent

   VCVTPS2QQ m512i _mm512_cvtps_epi64( m512 a);

   VCVTPS2QQ m512i _mm512_mask_cvtps_epi64( m512i s, mmask16 k, m512 a); VCVTPS2QQ m512i _mm512_maskz_cvtps_epi64( mmask16 k, m512 a); VCVTPS2QQ m512i _mm512_cvt_roundps_epi64( m512 a, int r);

   VCVTPS2QQ m512i _mm512_mask_cvt_roundps_epi64( m512i s, mmask16 k, m512 a, int r); VCVTPS2QQ m512i _mm512_maskz_cvt_roundps_epi64( mmask16 k, m512 a, int r); VCVTPS2QQ m256i _mm256_cvtps_epi64( m256 a);

   VCVTPS2QQ m256i _mm256_mask_cvtps_epi64( m256i s, mmask8 k, m256 a); VCVTPS2QQ m256i _mm256_maskz_cvtps_epi64( mmask8 k, m256 a); VCVTPS2QQ m128i _mm_cvtps_epi64( m128 a);

   VCVTPS2QQ m128i _mm_mask_cvtps_epi64( m128i s, mmask8 k, m128 a); VCVTPS2QQ m128i _mm_maskz_cvtps_epi64( mmask8 k, m128 a);

   
   

   SIMD Floating-Point Exceptions

   Invalid, Precision

   
   

   Other Exceptions

   EVEX-encoded instructions, see Exceptions Type E3

   #UD If EVEX.vvvv != 1111B.

   
   

   VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values

   Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
   EVEX.128.66.0F.W0 79 /r VCVTPS2UQQ xmm1 {k1}{z}, xmm2/m64/m32bcst	A	V/V	AVX512VL AVX512DQ	Convert two packed single precision floating-point values from zmm2/m64/m32bcst to two packed unsigned quadword values in zmm1 subject to writemask k1.
   EVEX.256.66.0F.W0 79 /r VCVTPS2UQQ ymm1 {k1}{z}, xmm2/m128/m32bcst	A	V/V	AVX512VL AVX512DQ	Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed unsigned quadword values in ymm1 subject to writemask k1.
   EVEX.512.66.0F.W0 79 /r VCVTPS2UQQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er}	A	V/V	AVX512DQ	Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed unsigned quadword values in zmm1 subject to writemask k1.

   
   

   Instruction Operand Encoding

   Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
   A	Half	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

   Description

   Converts up to eight packed single-precision floating-point values in the source operand to unsigned quadword integers in the destination operand.

   When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

   The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina- tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.

   EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

   
   

   
   

   Operation

   VCVTPS2UQQ (EVEX encoded versions) when src operand is a register

   (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL == 512) AND (EVEX.b == 1)

   THEN

   SET_RM(EVEX.RC);

   ELSE

   SET_RM(MXCSR.RM);

   FI;

   FOR j  0 TO KL-1

   i  j * 64 k  j * 32

   IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

   Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k]) ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+63:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   VCVTPS2UQQ (EVEX encoded versions) when src operand is a memory source

   (KL, VL) = (2, 128), (4, 256), (8, 512)

   
   

   FOR j  0 TO KL-1

   i  j * 64 k  j * 32

   IF k1[j] OR *no writemask* THEN

   IF (EVEX.b == 1) THEN

   DEST[i+63:i] 

   Convert_Single_Precision_To_UQuadInteger(SRC[31:0]) ELSE

   DEST[i+63:i] 

   Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k]) FI;

   ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+63:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   
   

   Intel C/C++ Compiler Intrinsic Equivalent

   VCVTPS2UQQ m512i _mm512_cvtps_epu64( m512 a);

   VCVTPS2UQQ m512i _mm512_mask_cvtps_epu64( m512i s, mmask16 k, m512 a); VCVTPS2UQQ m512i _mm512_maskz_cvtps_epu64( mmask16 k, m512 a); VCVTPS2UQQ m512i _mm512_cvt_roundps_epu64( m512 a, int r);

   VCVTPS2UQQ m512i _mm512_mask_cvt_roundps_epu64( m512i s, mmask16 k, m512 a, int r); VCVTPS2UQQ m512i _mm512_maskz_cvt_roundps_epu64( mmask16 k, m512 a, int r); VCVTPS2UQQ m256i _mm256_cvtps_epu64( m256 a);

   VCVTPS2UQQ m256i _mm256_mask_cvtps_epu64( m256i s, mmask8 k, m256 a); VCVTPS2UQQ m256i _mm256_maskz_cvtps_epu64( mmask8 k, m256 a); VCVTPS2UQQ m128i _mm_cvtps_epu64( m128 a);

   VCVTPS2UQQ m128i _mm_mask_cvtps_epu64( m128i s, mmask8 k, m128 a); VCVTPS2UQQ m128i _mm_maskz_cvtps_epu64( mmask8 k, m128 a);

   
   

   SIMD Floating-Point Exceptions

   Invalid, Precision

   
   

   Other Exceptions

   EVEX-encoded instructions, see Exceptions Type E3

   #UD If EVEX.vvvv != 1111B.

   
   

   VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values

   Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
   EVEX.128.F3.0F.W1 E6 /r VCVTQQ2PD xmm1 {k1}{z}, xmm2/m128/m64bcst	A	V/V	AVX512VL AVX512DQ	Convert two packed quadword integers from xmm2/m128/m64bcst to packed double-precision floating- point values in xmm1 with writemask k1.
   EVEX.256.F3.0F.W1 E6 /r VCVTQQ2PD ymm1 {k1}{z}, ymm2/m256/m64bcst	A	V/V	AVX512VL AVX512DQ	Convert four packed quadword integers from ymm2/m256/m64bcst to packed double-precision floating- point values in ymm1 with writemask k1.
   EVEX.512.F3.0F.W1 E6 /r VCVTQQ2PD zmm1 {k1}{z}, zmm2/m512/m64bcst{er}	A	V/V	AVX512DQ	Convert eight packed quadword integers from zmm2/m512/m64bcst to eight packed double-precision floating-point values in zmm1 with writemask k1.

   
   

   Instruction Operand Encoding

   Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
   A	Full	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

   Description

   Converts packed quadword integers in the source operand (second operand) to packed double-precision floating- point values in the destination operand (first operand).

   The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.

   EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

   
   

   Operation

   VCVTQQ2PD (EVEX2 encoded versions) when src operand is a register

   (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL == 512) AND (EVEX.b == 1)

   THEN

   SET_RM(EVEX.RC);

   ELSE

   SET_RM(MXCSR.RM);

   FI;

   
   

   FOR j  0 TO KL-1

   i  j * 64

   IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

   Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i]) ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+63:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   
   

   VCVTQQ2PD (EVEX encoded versions) when src operand is a memory source

   (KL, VL) = (2, 128), (4, 256), (8, 512)

   FOR j  0 TO KL-1

   i  j * 64

   IF k1[j] OR *no writemask* THEN

   IF (EVEX.b == 1) THEN

   DEST[i+63:i] 

   Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[63:0]) ELSE

   DEST[i+63:i] 

   Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i]) FI;

   ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

   ELSE ; zeroing-masking

   DEST[i+63:i]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL]  0

   
   

   Intel C/C++ Compiler Intrinsic Equivalent

   VCVTQQ2PD m512d _mm512_cvtepi64_pd( m512i a);

   VCVTQQ2PD m512d _mm512_mask_cvtepi64_pd( m512d s, mmask16 k, m512i a); VCVTQQ2PD m512d _mm512_maskz_cvtepi64_pd( mmask16 k, m512i a); VCVTQQ2PD m512d _mm512_cvt_roundepi64_pd( m512i a, int r);

   VCVTQQ2PD m512d _mm512_mask_cvt_roundepi64_pd( m512d s, mmask8 k, m512i a, int r); VCVTQQ2PD m512d _mm512_maskz_cvt_roundepi64_pd( mmask8 k, m512i a, int r); VCVTQQ2PD m256d _mm256_mask_cvtepi64_pd( m256d s, mmask8 k, m256i a); VCVTQQ2PD m256d _mm256_maskz_cvtepi64_pd( mmask8 k, m256i a);

   VCVTQQ2PD m128d _mm_mask_cvtepi64_pd( m128d s, mmask8 k, m128i a); VCVTQQ2PD m128d _mm_maskz_cvtepi64_pd( mmask8 k, m128i a);

   
   

   SIMD Floating-Point Exceptions

   Precision

   
   

   Other Exceptions

   EVEX-encoded instructions, see Exceptions Type E2

   #UD If EVEX.vvvv != 1111B.

   
   

   VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values

   Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
   EVEX.128.0F.W1 5B /r VCVTQQ2PS xmm1 {k1}{z}, xmm2/m128/m64bcst	A	V/V	AVX512VL AVX512DQ	Convert two packed quadword integers from xmm2/mem to packed single-precision floating-point values in xmm1 with writemask k1.
   EVEX.256.0F.W1 5B /r VCVTQQ2PS xmm1 {k1}{z}, ymm2/m256/m64bcst	A	V/V	AVX512VL AVX512DQ	Convert four packed quadword integers from ymm2/mem to packed single-precision floating-point values in xmm1 with writemask k1.
   EVEX.512.0F.W1 5B /r VCVTQQ2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er}	A	V/V	AVX512DQ	Convert eight packed quadword integers from zmm2/mem to eight packed single-precision floating-point values in ymm1 with writemask k1.

   
   

   Instruction Operand Encoding

   Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
   A	Full	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

   Description

   Converts packed quadword integers in the source operand (second operand) to packed single-precision floating- point values in the destination operand (first operand).

   The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation is a YMM/XMM/XMM (lower 64 bits) register conditionally updated with writemask k1.

   EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

   
   

   Operation

   VCVTQQ2PS (EVEX encoded versions) when src operand is a register

   (KL, VL) = (2, 128), (4, 256), (8, 512)

   
   

   FOR j  0 TO KL-1

   i  j * 64 k  j * 32

   IF k1[j] OR *no writemask* THEN DEST[k+31:k] 

   Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i]) ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[k+31:k] remains unchanged*

   ELSE ; zeroing-masking

   DEST[k+31:k]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL/2]  0

   
   

   
   

   VCVTQQ2PS (EVEX encoded versions) when src operand is a memory source

   (KL, VL) = (2, 128), (4, 256), (8, 512)

   
   

   FOR j  0 TO KL-1

   i  j * 64 k  j * 32

   IF k1[j] OR *no writemask* THEN

   IF (EVEX.b == 1) THEN

   DEST[k+31:k] 

   Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[63:0]) ELSE

   DEST[k+31:k] 

   Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i]) FI;

   ELSE

   IF *merging-masking* ; merging-masking THEN *DEST[k+31:k] remains unchanged*

   ELSE ; zeroing-masking

   DEST[k+31:k]  0

   FI

   FI;

   ENDFOR

   DEST[MAXVL-1:VL/2]  0

   
   

   Intel C/C++ Compiler Intrinsic Equivalent

   VCVTQQ2PS m256 _mm512_cvtepi64_ps( m512i a);

   VCVTQQ2PS m256 _mm512_mask_cvtepi64_ps( m256 s, mmask16 k, m512i a); VCVTQQ2PS m256 _mm512_maskz_cvtepi64_ps( mmask16 k, m512i a); VCVTQQ2PS m256 _mm512_cvt_roundepi64_ps( m512i a, int r);

   VCVTQQ2PS m256 _mm512_mask_cvt_roundepi_ps( m256 s, mmask8 k, m512i a, int r); VCVTQQ2PS m256 _mm512_maskz_cvt_roundepi64_ps( mmask8 k, m512i a, int r); VCVTQQ2PS m128 _mm256_cvtepi64_ps( m256i a);

   VCVTQQ2PS m128 _mm256_mask_cvtepi64_ps( m128 s, mmask8 k, m256i a); VCVTQQ2PS m128 _mm256_maskz_cvtepi64_ps( mmask8 k, m256i a); VCVTQQ2PS m128 _mm_cvtepi64_ps( m128i a);

   VCVTQQ2PS m128 _mm_mask_cvtepi64_ps( m128 s, mmask8 k, m128i a); VCVTQQ2PS m128 _mm_maskz_cvtepi64_ps( mmask8 k, m128i a);

   
   

   SIMD Floating-Point Exceptions

   Precision

   
   

   Other Exceptions

   EVEX-encoded instructions, see Exceptions Type E2

   #UD If EVEX.vvvv != 1111B.

   
   

   VCVTSD2USI—Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer

   Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
   EVEX.LIG.F2.0F.W0 79 /r VCVTSD2USI r32, xmm1/m64{er}	A	V/V	AVX512F	Convert one double-precision floating-point value from xmm1/m64 to one unsigned doubleword integer r32.
   EVEX.LIG.F2.0F.W1 79 /r VCVTSD2USI r64, xmm1/m64{er}	A	V/N.E.1	AVX512F	Convert one double-precision floating-point value from xmm1/m64 to one unsigned quadword integer zero- extended into r64.

   NOTES:

2. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Description

Converts a double-precision floating-point value in the source operand (the second operand) to an unsigned doubleword integer in the destination operand (the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the double-precision floating-point value is contained in the low quadword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

Operation

VCVTSD2USI (EVEX encoded version)

IF (SRC *is register*) AND (EVEX.b = 1) THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

IF 64-Bit Mode and OperandSize = 64

THEN DEST[63:0]  Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]); ELSE DEST[31:0]  Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);

FI

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSD2USI unsigned int _mm_cvtsd_u32( m128d); VCVTSD2USI unsigned int _mm_cvt_roundsd_u32( m128d, int r); VCVTSD2USI unsigned int64 _mm_cvtsd_u64( m128d);

VCVTSD2USI unsigned int64 _mm_cvt_roundsd_u64( m128d, int r);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E3NF.

VCVTSS2USI—Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer

NOTES:

1. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Description

Converts a single-precision floating-point value in the source operand (the second operand) to an unsigned double- word integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a memory location. The destination operand is a general- purpose register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode. Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTSS2USI (EVEX encoded version)

IF (SRC *is register*) AND (EVEX.b = 1) THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

IF 64-bit Mode and OperandSize = 64 THEN

DEST[63:0]  Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]); ELSE

DEST[31:0]  Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);

FI;

Intel C/C++ Compiler Intrinsic Equivalent

VCVTSS2USI unsigned _mm_cvtss_u32( m128 a); VCVTSS2USI unsigned _mm_cvt_roundss_u32( m128 a, int r); VCVTSS2USI unsigned int64 _mm_cvtss_u64( m128 a);

VCVTSS2USI unsigned int64 _mm_cvt_roundss_u64( m128 a, int r);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E3NF.

VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers

Instruction Operand Encoding

Description

Converts with truncation packed double-precision floating-point values in the source operand (second operand) to packed quadword integers in the destination operand (first operand).

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTTPD2QQ (EVEX encoded version) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTTPD2QQ (EVEX encoded version) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b == 1) THEN

DEST[i+63:i]  Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[63:0]) ELSE

DEST[i+63:i]  Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])

FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPD2QQ m512i _mm512_cvttpd_epi64( m512d a);

VCVTTPD2QQ m512i _mm512_mask_cvttpd_epi64( m512i s, mmask8 k, m512d a); VCVTTPD2QQ m512i _mm512_maskz_cvttpd_epi64( mmask8 k, m512d a); VCVTTPD2QQ m512i _mm512_cvtt_roundpd_epi64( m512d a, int sae);

VCVTTPD2QQ m512i _mm512_mask_cvtt_roundpd_epi64( m512i s, mmask8 k, m512d a, int sae); VCVTTPD2QQ m512i _mm512_maskz_cvtt_roundpd_epi64( mmask8 k, m512d a, int sae); VCVTTPD2QQ m256i _mm256_mask_cvttpd_epi64( m256i s, mmask8 k, m256d a);

VCVTTPD2QQ m256i _mm256_maskz_cvttpd_epi64( mmask8 k, m256d a); VCVTTPD2QQ m128i _mm_mask_cvttpd_epi64( m128i s, mmask8 k, m128d a); VCVTTPD2QQ m128i _mm_maskz_cvttpd_epi64( mmask8 k, m128d a);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.

#UD If EVEX.vvvv != 1111B.

VCVTTPD2UDQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers

Instruction Operand Encoding

Description

Converts with truncation packed double-precision floating-point values in the source operand (the second operand) to packed unsigned doubleword integers in the destination operand (the first operand).

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are zeroed.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTTPD2UDQ (EVEX encoded versions) when src2 operand is a register

(KL, VL) = (2, 128), (4, 256),(8, 512)

FOR j  0 TO KL-1

i  j * 32 k  j * 64

IF k1[j] OR *no writemask* THEN

DEST[i+31:i] 

Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2]  0

VCVTTPD2UDQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256),(8, 512)

FOR j  0 TO KL-1

i  j * 32 k  j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) THEN

DEST[i+31:i] 

Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]) ELSE

DEST[i+31:i] 

Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPD2UDQ m256i _mm512_cvttpd_epu32( m512d a);

VCVTTPD2UDQ m256i _mm512_mask_cvttpd_epu32( m256i s, mmask8 k, m512d a); VCVTTPD2UDQ m256i _mm512_maskz_cvttpd_epu32( mmask8 k, m512d a); VCVTTPD2UDQ m256i _mm512_cvtt_roundpd_epu32( m512d a, int sae);

VCVTTPD2UDQ m256i _mm512_mask_cvtt_roundpd_epu32( m256i s, mmask8 k, m512d a, int sae); VCVTTPD2UDQ m256i _mm512_maskz_cvtt_roundpd_epu32( mmask8 k, m512d a, int sae); VCVTTPD2UDQ m128i _mm256_mask_cvttpd_epu32( m128i s, mmask8 k, m256d a); VCVTTPD2UDQ m128i _mm256_maskz_cvttpd_epu32( mmask8 k, m256d a);

VCVTTPD2UDQ m128i _mm_mask_cvttpd_epu32( m128i s, mmask8 k, m128d a); VCVTTPD2UDQ m128i _mm_maskz_cvttpd_epu32( mmask8 k, m128d a);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.

#UD If EVEX.vvvv != 1111B.

VCVTTPD2UQQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers

Instruction Operand Encoding

Description

Converts with truncation packed double-precision floating-point values in the source operand (second operand) to packed unsigned quadword integers in the destination operand (first operand).

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTTPD2UQQ (EVEX encoded versions) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTTPD2UQQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b == 1) THEN

DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[63:0]) ELSE

DEST[i+63:i] 

Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPD2UQQ _mm<size>[_mask[z]]_cvtt[_round]pd_epu64 VCVTTPD2UQQ m512i _mm512_cvttpd_epu64( m512d a);

VCVTTPD2UQQ m512i _mm512_mask_cvttpd_epu64( m512i s, mmask8 k, m512d a); VCVTTPD2UQQ m512i _mm512_maskz_cvttpd_epu64( mmask8 k, m512d a); VCVTTPD2UQQ m512i _mm512_cvtt_roundpd_epu64( m512d a, int sae);

VCVTTPD2UQQ m512i _mm512_mask_cvtt_roundpd_epu64( m512i s, mmask8 k, m512d a, int sae); VCVTTPD2UQQ m512i _mm512_maskz_cvtt_roundpd_epu64( mmask8 k, m512d a, int sae); VCVTTPD2UQQ m256i _mm256_mask_cvttpd_epu64( m256i s, mmask8 k, m256d a); VCVTTPD2UQQ m256i _mm256_maskz_cvttpd_epu64( mmask8 k, m256d a);

VCVTTPD2UQQ m128i _mm_mask_cvttpd_epu64( m128i s, mmask8 k, m128d a); VCVTTPD2UQQ m128i _mm_maskz_cvttpd_epu64( mmask8 k, m128d a);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.

#UD If EVEX.vvvv != 1111B.

VCVTTPS2UDQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values

Instruction Operand Encoding

Description

Converts with truncation packed single-precision floating-point values in the source operand to sixteen unsigned doubleword integers in the destination operand.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTTPS2UDQ (EVEX encoded versions) when src operand is a register

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j  0 TO KL-1

i  j * 32

IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTTPS2UDQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j  0 TO KL-1

i  j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) THEN

DEST[i+31:i] 

Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]) ELSE

DEST[i+31:i] 

Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPS2UDQ m512i _mm512_cvttps_epu32( m512 a);

VCVTTPS2UDQ m512i _mm512_mask_cvttps_epu32( m512i s, mmask16 k, m512 a); VCVTTPS2UDQ m512i _mm512_maskz_cvttps_epu32( mmask16 k, m512 a); VCVTTPS2UDQ m512i _mm512_cvtt_roundps_epu32( m512 a, int sae);

VCVTTPS2UDQ m512i _mm512_mask_cvtt_roundps_epu32( m512i s, mmask16 k, m512 a, int sae); VCVTTPS2UDQ m512i _mm512_maskz_cvtt_roundps_epu32( mmask16 k, m512 a, int sae); VCVTTPS2UDQ m256i _mm256_mask_cvttps_epu32( m256i s, mmask8 k, m256 a);

VCVTTPS2UDQ m256i _mm256_maskz_cvttps_epu32( mmask8 k, m256 a); VCVTTPS2UDQ m128i _mm_mask_cvttps_epu32( m128i s, mmask8 k, m128 a); VCVTTPS2UDQ m128i _mm_maskz_cvttps_epu32( mmask8 k, m128 a);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.

#UD If EVEX.vvvv != 1111B.

VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values

Instruction Operand Encoding

Description

Converts with truncation packed single-precision floating-point values in the source operand to eight signed quad- word integers in the destination operand.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.

EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit memory location. The destination operation is a vector register conditionally updated with writemask k1.

Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTTPS2QQ (EVEX encoded versions) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64 k  j * 32

IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTTPS2QQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64 k  j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b == 1) THEN

DEST[i+63:i] 

Convert_Single_Precision_To_QuadInteger_Truncate(SRC[31:0]) ELSE

DEST[i+63:i] 

Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPS2QQ m512i _mm512_cvttps_epi64( m256 a);

VCVTTPS2QQ m512i _mm512_mask_cvttps_epi64( m512i s, mmask16 k, m256 a); VCVTTPS2QQ m512i _mm512_maskz_cvttps_epi64( mmask16 k, m256 a); VCVTTPS2QQ m512i _mm512_cvtt_roundps_epi64( m256 a, int sae);

VCVTTPS2QQ m512i _mm512_mask_cvtt_roundps_epi64( m512i s, mmask16 k, m256 a, int sae); VCVTTPS2QQ m512i _mm512_maskz_cvtt_roundps_epi64( mmask16 k, m256 a, int sae); VCVTTPS2QQ m256i _mm256_mask_cvttps_epi64( m256i s, mmask8 k, m128 a);

VCVTTPS2QQ m256i _mm256_maskz_cvttps_epi64( mmask8 k, m128 a); VCVTTPS2QQ m128i _mm_mask_cvttps_epi64( m128i s, mmask8 k, m128 a); VCVTTPS2QQ m128i _mm_maskz_cvttps_epi64( mmask8 k, m128 a);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E3.

#UD If EVEX.vvvv != 1111B.

VCVTTPS2UQQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values

Instruction Operand Encoding

Description

Converts with truncation up to eight packed single-precision floating-point values in the source operand to unsigned quadword integers in the destination operand.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit memory location. The destination operation is a vector register conditionally updated with writemask k1.

Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation

VCVTTPS2UQQ (EVEX encoded versions) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64 k  j * 32

IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTTPS2UQQ (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64 k  j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b == 1) THEN

DEST[i+63:i] 

Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[31:0]) ELSE

DEST[i+63:i] 

Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPS2UQQ _mm<size>[_mask[z]]_cvtt[_round]ps_epu64 VCVTTPS2UQQ m512i _mm512_cvttps_epu64( m256 a);

VCVTTPS2UQQ m512i _mm512_mask_cvttps_epu64( m512i s, mmask16 k, m256 a); VCVTTPS2UQQ m512i _mm512_maskz_cvttps_epu64( mmask16 k, m256 a); VCVTTPS2UQQ m512i _mm512_cvtt_roundps_epu64( m256 a, int sae);

VCVTTPS2UQQ m512i _mm512_mask_cvtt_roundps_epu64( m512i s, mmask16 k, m256 a, int sae); VCVTTPS2UQQ m512i _mm512_maskz_cvtt_roundps_epu64( mmask16 k, m256 a, int sae); VCVTTPS2UQQ m256i _mm256_mask_cvttps_epu64( m256i s, mmask8 k, m128 a);

VCVTTPS2UQQ m256i _mm256_maskz_cvttps_epu64( mmask8 k, m128 a); VCVTTPS2UQQ m128i _mm_mask_cvttps_epu64( m128i s, mmask8 k, m128 a); VCVTTPS2UQQ m128i _mm_maskz_cvttps_epu64( mmask8 k, m128 a);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E3.

#UD If EVEX.vvvv != 1111B.

VCVTTSD2USI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer

NOTES:

1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Description

Converts with truncation a double-precision floating-point value in the source operand (the second operand) to an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the double-precision floating- point value is contained in the low quadword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.

Operation

VCVTTSD2USI (EVEX encoded version)

IF 64-Bit Mode and OperandSize = 64

THEN DEST[63:0]  Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]); ELSE DEST[31:0]  Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);

FI

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTSD2USI unsigned int _mm_cvttsd_u32( m128d); VCVTTSD2USI unsigned int _mm_cvtt_roundsd_u32( m128d, int sae); VCVTTSD2USI unsigned int64 _mm_cvttsd_u64( m128d);

VCVTTSD2USI unsigned int64 _mm_cvtt_roundsd_u64( m128d, int sae);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E3NF.

VCVTTSS2USI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer

NOTES:

1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Description

Converts with truncation a single-precision floating-point value in the source operand (the second operand) to an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.

EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode. Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTTSS2USI (EVEX encoded version) IF 64-bit Mode and OperandSize = 64 THEN

DEST[63:0]  Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]); ELSE

DEST[31:0]  Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);

FI;

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTSS2USI unsigned int _mm_cvttss_u32( m128 a);

VCVTTSS2USI unsigned int _mm_cvtt_roundss_u32( m128 a, int sae); VCVTTSS2USI unsigned int64 _mm_cvttss_u64( m128 a);

VCVTTSS2USI unsigned int64 _mm_cvtt_roundss_u64( m128 a, int sae);

SIMD Floating-Point Exceptions

Invalid, Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E3NF.

VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values

Instruction Operand Encoding

Description

Converts packed unsigned doubleword integers in the source operand (second operand) to packed double-preci- sion floating-point values in the destination operand (first operand).

The source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Attempt to encode this instruction with EVEX embedded rounding is ignored. Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTUDQ2PD (EVEX encoded versions) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64 k  j * 32

IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTUDQ2PD (EVEX encoded versions) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64 k  j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) THEN

DEST[i+63:i] 

Convert_UInteger_To_Double_Precision_Floating_Point(SRC[31:0]) ELSE

DEST[i+63:i] 

Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTUDQ2PD m512d _mm512_cvtepu32_pd( m256i a);

VCVTUDQ2PD m512d _mm512_mask_cvtepu32_pd( m512d s, mmask8 k, m256i a); VCVTUDQ2PD m512d _mm512_maskz_cvtepu32_pd( mmask8 k, m256i a); VCVTUDQ2PD m256d _mm256_cvtepu32_pd( m128i a);

VCVTUDQ2PD m256d _mm256_mask_cvtepu32_pd( m256d s, mmask8 k, m128i a); VCVTUDQ2PD m256d _mm256_maskz_cvtepu32_pd( mmask8 k, m128i a); VCVTUDQ2PD m128d _mm_cvtepu32_pd( m128i a);

VCVTUDQ2PD m128d _mm_mask_cvtepu32_pd( m128d s, mmask8 k, m128i a); VCVTUDQ2PD m128d _mm_maskz_cvtepu32_pd( mmask8 k, m128i a);

SIMD Floating-Point Exceptions

None

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E5.

#UD If EVEX.vvvv != 1111B.

VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values

Instruction Operand Encoding

Description

Converts packed unsigned doubleword integers in the source operand (second operand) to single-precision floating-point values in the destination operand (first operand).

The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTUDQ2PS (EVEX encoded version) when src operand is a register

(KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j  0 TO KL-1

i  j * 32

IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTUDQ2PS (EVEX encoded version) when src operand is a memory source

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j  0 TO KL-1

i  j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) THEN

DEST[i+31:i] 

Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0]) ELSE

DEST[i+31:i] 

Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTUDQ2PS m512 _mm512_cvtepu32_ps( m512i a);

VCVTUDQ2PS m512 _mm512_mask_cvtepu32_ps( m512 s, mmask16 k, m512i a); VCVTUDQ2PS m512 _mm512_maskz_cvtepu32_ps( mmask16 k, m512i a); VCVTUDQ2PS m512 _mm512_cvt_roundepu32_ps( m512i a, int r);

VCVTUDQ2PS m512 _mm512_mask_cvt_roundepu32_ps( m512 s, mmask16 k, m512i a, int r); VCVTUDQ2PS m512 _mm512_maskz_cvt_roundepu32_ps( mmask16 k, m512i a, int r); VCVTUDQ2PS m256 _mm256_cvtepu32_ps( m256i a);

VCVTUDQ2PS m256 _mm256_mask_cvtepu32_ps( m256 s, mmask8 k, m256i a); VCVTUDQ2PS m256 _mm256_maskz_cvtepu32_ps( mmask8 k, m256i a); VCVTUDQ2PS m128 _mm_cvtepu32_ps( m128i a);

VCVTUDQ2PS m128 _mm_mask_cvtepu32_ps( m128 s, mmask8 k, m128i a); VCVTUDQ2PS m128 _mm_maskz_cvtepu32_ps( mmask8 k, m128i a);

SIMD Floating-Point Exceptions

Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.

#UD If EVEX.vvvv != 1111B.

VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values

Instruction Operand Encoding

Description

Converts packed unsigned quadword integers in the source operand (second operand) to packed double-precision floating-point values in the destination operand (first operand).

The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTUQQ2PD (EVEX encoded version) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL == 512) AND (EVEX.b == 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

VCVTUQQ2PD (EVEX encoded version) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b == 1) THEN

DEST[i+63:i] 

Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[63:0]) ELSE

DEST[i+63:i] 

Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+63:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTUQQ2PD m512d _mm512_cvtepu64_ps( m512i a);

VCVTUQQ2PD m512d _mm512_mask_cvtepu64_ps( m512d s, mmask8 k, m512i a); VCVTUQQ2PD m512d _mm512_maskz_cvtepu64_ps( mmask8 k, m512i a); VCVTUQQ2PD m512d _mm512_cvt_roundepu64_ps( m512i a, int r);

VCVTUQQ2PD m512d _mm512_mask_cvt_roundepu64_ps( m512d s, mmask8 k, m512i a, int r); VCVTUQQ2PD m512d _mm512_maskz_cvt_roundepu64_ps( mmask8 k, m512i a, int r); VCVTUQQ2PD m256d _mm256_cvtepu64_ps( m256i a);

VCVTUQQ2PD m256d _mm256_mask_cvtepu64_ps( m256d s, mmask8 k, m256i a); VCVTUQQ2PD m256d _mm256_maskz_cvtepu64_ps( mmask8 k, m256i a); VCVTUQQ2PD m128d _mm_cvtepu64_ps( m128i a);

VCVTUQQ2PD m128d _mm_mask_cvtepu64_ps( m128d s, mmask8 k, m128i a); VCVTUQQ2PD m128d _mm_maskz_cvtepu64_ps( mmask8 k, m128i a);

SIMD Floating-Point Exceptions

Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.

#UD If EVEX.vvvv != 1111B.

VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values

Instruction Operand Encoding

Description

Converts packed unsigned quadword integers in the source operand (second operand) to single-precision floating- point values in the destination operand (first operand).

EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation

VCVTUQQ2PS (EVEX encoded version) when src operand is a register

(KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

FOR j  0 TO KL-1

i  j * 32 k  j * 64

IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k]) ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2]  0

VCVTUQQ2PS (EVEX encoded version) when src operand is a memory source

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j  0 TO KL-1

i  j * 32 k  j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) THEN

DEST[i+31:i] 

Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[63:0]) ELSE

DEST[i+31:i] 

Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k]) FI;

ELSE

IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

ELSE ; zeroing-masking

DEST[i+31:i]  0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL/2]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTUQQ2PS m256 _mm512_cvtepu64_ps( m512i a);

VCVTUQQ2PS m256 _mm512_mask_cvtepu64_ps( m256 s, mmask8 k, m512i a); VCVTUQQ2PS m256 _mm512_maskz_cvtepu64_ps( mmask8 k, m512i a); VCVTUQQ2PS m256 _mm512_cvt_roundepu64_ps( m512i a, int r);

VCVTUQQ2PS m256 _mm512_mask_cvt_roundepu64_ps( m256 s, mmask8 k, m512i a, int r); VCVTUQQ2PS m256 _mm512_maskz_cvt_roundepu64_ps( mmask8 k, m512i a, int r); VCVTUQQ2PS m128 _mm256_cvtepu64_ps( m256i a);

VCVTUQQ2PS m128 _mm256_mask_cvtepu64_ps( m128 s, mmask8 k, m256i a); VCVTUQQ2PS m128 _mm256_maskz_cvtepu64_ps( mmask8 k, m256i a); VCVTUQQ2PS m128 _mm_cvtepu64_ps( m128i a);

VCVTUQQ2PS m128 _mm_mask_cvtepu64_ps( m128 s, mmask8 k, m128i a); VCVTUQQ2PS m128 _mm_maskz_cvtepu64_ps( mmask8 k, m128i a);

SIMD Floating-Point Exceptions

Precision

Other Exceptions

EVEX-encoded instructions, see Exceptions Type E2.

#UD If EVEX.vvvv != 1111B.

VCVTUSI2SD—Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value

NOTES:

1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Description

Converts an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the second source operand to a double-precision floating-point value in the destination operand. The result is stored in the low quadword of the destination operand. When conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.

The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of the XMM register destination are copied from corre- sponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.

EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.

EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.

Operation

VCVTUSI2SD (EVEX encoded version)

IF (SRC2 *is register*) AND (EVEX.b = 1) THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

IF 64-Bit Mode And OperandSize = 64 THEN

DEST[63:0]  Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[63:0]); ELSE

DEST[63:0]  Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[31:0]);

FI;

DEST[127:64]  SRC1[127:64] DEST[MAXVL-1:128]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTUSI2SD m128d _mm_cvtu32_sd( m128d s, unsigned a); VCVTUSI2SD m128d _mm_cvtu64_sd( m128d s, unsigned int64 a);

VCVTUSI2SD m128d _mm_cvt_roundu64_sd( m128d s, unsigned int64 a, int r);

SIMD Floating-Point Exceptions

Precision

Other Exceptions

See Exceptions Type E3NF if W1, else type E10NF.

VCVTUSI2SS—Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value

NOTES:

1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Description

Converts a unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the source operand (second operand) to a single-precision floating-point value in the destination operand (first operand). The source operand can be a general-purpose register or a memory location. The destination operand is an XMM register. The result is stored in the low doubleword of the destination operand. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits.

The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of the XMM register destination are copied from corre- sponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.

EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.

Operation

VCVTUSI2SS (EVEX encoded version)

IF (SRC2 *is register*) AND (EVEX.b = 1) THEN

SET_RM(EVEX.RC);

ELSE

SET_RM(MXCSR.RM);

FI;

IF 64-Bit Mode And OperandSize = 64 THEN

DEST[31:0]  Convert_UInteger_To_Single_Precision_Floating_Point(SRC[63:0]); ELSE

DEST[31:0]  Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0]);

FI;

DEST[127:32]  SRC1[127:32] DEST[MAXVL-1:128]  0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTUSI2SS m128 _mm_cvtu32_ss( m128 s, unsigned a); VCVTUSI2SS m128 _mm_cvt_roundu32_ss( m128 s, unsigned a, int r); VCVTUSI2SS m128 _mm_cvtu64_ss( m128 s, unsigned int64 a);

VCVTUSI2SS m128 _mm_cvt_roundu64_ss( m128 s, unsigned int64 a, int r);

SIMD Floating-Point Exceptions

Precision

Other Exceptions

See Exceptions Type E3NF.

VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes

Instruction Operand Encoding

Description

Compute packed SAD (sum of absolute differences) word results of unsigned bytes from two 32-bit dword elements. Packed SAD word results are calculated in multiples of qword superblocks, producing 4 SAD word results in each 64-bit superblock of the destination register.

Within each super block of packed word results, the SAD results from two 32-bit dword elements are calculated as follows:

• The lower two word results are calculated each from the SAD operation between a sliding dword element within a qword superblock from an intermediate vector with a stationary dword element in the corresponding qword superblock of the first source operand. The intermediate vector, see “Tmp1” in Figure 5-8, is constructed from the second source operand the imm8 byte as shuffle control to select dword elements within a 128-bit lane of the second source operand. The two sliding dword elements in a qword superblock of Tmp1 are located at byte offset 0 and 1 within the superblock, respectively. The stationary dword element in the qword superblock from the first source operand is located at byte offset 0.

• The next two word results are calculated each from the SAD operation between a sliding dword element within a qword superblock from the intermediate vector Tmp1 with a second stationary dword element in the corre- sponding qword superblock of the first source operand. The two sliding dword elements in a qword superblock of Tmp1 are located at byte offset 2and 3 within the superblock, respectively. The stationary dword element in the qword superblock from the first source operand is located at byte offset 4.

• The intermediate vector is constructed in 128-bits lanes. Within each 128-bit lane, each dword element of the intermediate vector is selected by a two-bit field within the imm8 byte on the corresponding 128-bits of the second source operand. The imm8 byte serves as dword shuffle control within each 128-bit lanes of the inter- mediate vector and the second source operand, similarly to PSHUFD.

  The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1 at 16-bit word granularity.

  
  

  

  127+128*n

  95+128*n

  63+128*n

  31+128*n

  128*n

  128-bit Lane of Src2

  DW3 DW2 DW1 DW0

  
  

  
  

  imm8 shuffle control

  
  

  7 5 3 1 0

  00B: DW0

  01B: DW1

  10B: DW2

  11B: DW3

  
  

  
  

  128-bit Lane of Tmp1

  127+128*n

  95+128*n

  63+128*n

  31+128*n

  
  

  Tmp1 qword superblock

  128*n

  
  

  55	47	39	31 24		39	31	23	15 8
  63	55	47	39 32	Tmp1 sliding dword	31	23	15	7 0	Tmp1 sliding dword

  _

  abs

  _

  abs

  _

  abs

  _

  abs

  Src1 stationary dword 1

  _

  abs

  _

  abs

  _

  abs

  _

  abs

  Src1 stationary dword 0

  
  

  + 47

  
  

  63

  
  

  _

  
  

  39 31

  
  

  55 47

  
  

  _ _

  
  

  23 16

  
  

  39 32

  
  

  _

  
  

  Tmp1 sliding dword

  
  

  Src1 stationary dword 1

  +

  31 23

  
  

  31 23

  
  

  _ _

  
  

  15 7 0

  
  

  15 7 0

  
  

  _ _

  
  

  Tmp1 sliding dword

  
  

  Src1 stationary dword 0

  abs

  abs abs

  abs

  abs abs

  abs abs

  
  

  
  

  63

  Destination qword superblock

  +

  47 31

  
  

  +

  15 0

  
  

  Figure 5-8. 64-bit Super Block of SAD Operation in VDBPSADBW

  
  

  
  

  Operation

  VDBPSADBW (EVEX encoded versions)

  (KL, VL) = (8, 128), (16, 256), (32, 512)

  Selection of quadruplets:

  FOR I = 0 to VL step 128

  TMP1[I+31:I]  select (SRC2[I+127: I], imm8[1:0]) TMP1[I+63: I+32]  select (SRC2[I+127: I], imm8[3:2]) TMP1[I+95: I+64]  select (SRC2[I+127: I], imm8[5:4]) TMP1[I+127: I+96] select (SRC2[I+127: I], imm8[7:6])

  END FOR

  
  

  SAD of quadruplets:

  
  

  FOR I =0 to VL step 64

  TMP_DEST[I+15:I]  ABS(SRC1[I+7: I] - TMP1[I+7: I]) + ABS(SRC1[I+15: I+8]- TMP1[I+15: I+8]) + ABS(SRC1[I+23: I+16]- TMP1[I+23: I+16]) + ABS(SRC1[I+31: I+24]- TMP1[I+31: I+24])

  
  

  TMP_DEST[I+31: I+16] ABS(SRC1[I+7: I] - TMP1[I+15: I+8]) + ABS(SRC1[I+15: I+8]- TMP1[I+23: I+16]) + ABS(SRC1[I+23: I+16]- TMP1[I+31: I+24]) + ABS(SRC1[I+31: I+24]- TMP1[I+39: I+32])

  TMP_DEST[I+47: I+32] ABS(SRC1[I+39: I+32] - TMP1[I+23: I+16]) + ABS(SRC1[I+47: I+40]- TMP1[I+31: I+24]) +

  ABS(SRC1[I+55: I+48]- TMP1[I+39: I+32]) + ABS(SRC1[I+63: I+56]- TMP1[I+47: I+40])

  
  

  TMP_DEST[I+63: I+48] ABS(SRC1[I+39: I+32] - TMP1[I+31: I+24]) + ABS(SRC1[I+47: I+40] - TMP1[I+39: I+32]) +

  ABS(SRC1[I+55: I+48] - TMP1[I+47: I+40]) + ABS(SRC1[I+63: I+56] - TMP1[I+55: I+48])

  ENDFOR

  
  

  FOR j  0 TO KL-1

  i  j * 16

  IF k1[j] OR *no writemask*

  THEN DEST[i+15:i]  TMP_DEST[i+15:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+15:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+15:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VDBPSADBW m512i _mm512_dbsad_epu8( m512i a, m512i b);

  VDBPSADBW m512i _mm512_mask_dbsad_epu8( m512i s, mmask32 m, m512i a, m512i b); VDBPSADBW m512i _mm512_maskz_dbsad_epu8( mmask32 m, m512i a, m512i b); VDBPSADBW m256i _mm256_dbsad_epu8( m256i a, m256i b);

  VDBPSADBW m256i _mm256_mask_dbsad_epu8( m256i s, mmask16 m, m256i a, m256i b); VDBPSADBW m256i _mm256_maskz_dbsad_epu8( mmask16 m, m256i a, m256i b); VDBPSADBW m128i _mm_dbsad_epu8( m128i a, m128i b);

  VDBPSADBW m128i _mm_mask_dbsad_epu8( m128i s, mmask8 m, m128i a, m128i b); VDBPSADBW m128i _mm_maskz_dbsad_epu8( mmask8 m, m128i a, m128i b);

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type E4NF.nb.

  
  

  VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.128.66.0F38.W1 88 /r VEXPANDPD xmm1 {k1}{z}, xmm2/m128	A	V/V	AVX512VL AVX512F	Expand packed double-precision floating-point values from xmm2/m128 to xmm1 using writemask k1.
  EVEX.256.66.0F38.W1 88 /r VEXPANDPD ymm1 {k1}{z}, ymm2/m256	A	V/V	AVX512VL AVX512F	Expand packed double-precision floating-point values from ymm2/m256 to ymm1 using writemask k1.
  EVEX.512.66.0F38.W1 88 /r VEXPANDPD zmm1 {k1}{z}, zmm2/m512	A	V/V	AVX512F	Expand packed double-precision floating-point values from zmm2/m512 to zmm1 using writemask k1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Tuple1 Scalar	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

  Description

  Expand (load) up to 8/4/2, contiguous, double-precision floating-point values of the input vector in the source operand (the second operand) to sparse elements in the destination operand (the first operand) selected by the writemask k1.

  The destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.

  The input vector starts from the lowest element in the source operand. The writemask register k1 selects the desti- nation elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or zeroed, depending on EVEX.z.

  EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

  Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.

  
  

  Operation

  VEXPANDPD (EVEX encoded versions)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  k  0

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  DEST[i+63:i]  SRC[k+63:k];

  k  k + 64 ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VEXPANDPD m512d _mm512_mask_expand_pd( m512d s, mmask8 k, m512d a); VEXPANDPD m512d _mm512_maskz_expand_pd( mmask8 k, m512d a); VEXPANDPD m512d _mm512_mask_expandloadu_pd( m512d s, mmask8 k, void * a); VEXPANDPD m512d _mm512_maskz_expandloadu_pd( mmask8 k, void * a); VEXPANDPD m256d _mm256_mask_expand_pd( m256d s, mmask8 k, m256d a); VEXPANDPD m256d _mm256_maskz_expand_pd( mmask8 k, m256d a); VEXPANDPD m256d _mm256_mask_expandloadu_pd( m256d s, mmask8 k, void * a); VEXPANDPD m256d _mm256_maskz_expandloadu_pd( mmask8 k, void * a); VEXPANDPD m128d _mm_mask_expand_pd( m128d s, mmask8 k, m128d a); VEXPANDPD m128d _mm_maskz_expand_pd( mmask8 k, m128d a);

  VEXPANDPD m128d _mm_mask_expandloadu_pd( m128d s, mmask8 k, void * a); VEXPANDPD m128d _mm_maskz_expandloadu_pd( mmask8 k, void * a);

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type E4.nb.

  #UD If EVEX.vvvv != 1111B.

  
  

  VEXPANDPS—Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.128.66.0F38.W0 88 /r VEXPANDPS xmm1 {k1}{z}, xmm2/m128	A	V/V	AVX512VL AVX512F	Expand packed single-precision floating-point values from xmm2/m128 to xmm1 using writemask k1.
  EVEX.256.66.0F38.W0 88 /r VEXPANDPS ymm1 {k1}{z}, ymm2/m256	A	V/V	AVX512VL AVX512F	Expand packed single-precision floating-point values from ymm2/m256 to ymm1 using writemask k1.
  EVEX.512.66.0F38.W0 88 /r VEXPANDPS zmm1 {k1}{z}, zmm2/m512	A	V/V	AVX512F	Expand packed single-precision floating-point values from zmm2/m512 to zmm1 using writemask k1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Tuple1 Scalar	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

  Description

  Expand (load) up to 16/8/4, contiguous, single-precision floating-point values of the input vector in the source operand (the second operand) to sparse elements of the destination operand (the first operand) selected by the writemask k1.

  The destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.

  The input vector starts from the lowest element in the source operand. The writemask k1 selects the destination elements (a partial vector or sparse elements if less than 16 elements) to be replaced by the ascending elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or zeroed, depending on EVEX.z.

  EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

  Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.

  
  

  Operation

  VEXPANDPS (EVEX encoded versions)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  k  0

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  DEST[i+31:i]  SRC[k+31:k];

  k  k + 32 ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VEXPANDPS m512 _mm512_mask_expand_ps( m512 s, mmask16 k, m512 a); VEXPANDPS m512 _mm512_maskz_expand_ps( mmask16 k, m512 a); VEXPANDPS m512 _mm512_mask_expandloadu_ps( m512 s, mmask16 k, void * a); VEXPANDPS m512 _mm512_maskz_expandloadu_ps( mmask16 k, void * a); VEXPANDPD m256 _mm256_mask_expand_ps( m256 s, mmask8 k, m256 a); VEXPANDPD m256 _mm256_maskz_expand_ps( mmask8 k, m256 a);

  VEXPANDPD m256 _mm256_mask_expandloadu_ps( m256 s, mmask8 k, void * a); VEXPANDPD m256 _mm256_maskz_expandloadu_ps( mmask8 k, void * a); VEXPANDPD m128 _mm_mask_expand_ps( m128 s, mmask8 k, m128 a); VEXPANDPD m128 _mm_maskz_expand_ps( mmask8 k, m128 a);

  VEXPANDPD m128 _mm_mask_expandloadu_ps( m128 s, mmask8 k, void * a); VEXPANDPD m128 _mm_maskz_expandloadu_ps( mmask8 k, void * a);

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type E4.nb.

  #UD If EVEX.vvvv != 1111B.

  
  

  VERR/VERW—Verify a Segment for Reading or Writing

  Opcode	Instruction	Op/ En	64-Bit Mode	Compat/ Leg Mode	Description
  0F 00 /4	VERR r/m16	M	Valid	Valid	Set ZF=1 if segment specified with r/m16 can be read.
  0F 00 /5	VERW r/m16	M	Valid	Valid	Set ZF=1 if segment specified with r/m16 can be written.

  
  

  Instruction Operand Encoding

  Op/En	Operand 1	Operand 2	Operand 3	Operand 4
  M	ModRM:r/m (r)	NA	NA	NA

  
  

  Description

  Verifies whether the code or data segment specified with the source operand is readable (VERR) or writable (VERW) from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that contains the segment selector for the segment to be verified. If the segment is accessible and readable (VERR) or writable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segments are never verified as writable. This check cannot be performed on system segments.

  To set the ZF flag, the following conditions must be met:

• The segment selector is not NULL.

• The selector must denote a descriptor within the bounds of the descriptor table (GDT or LDT).

• The selector must denote the descriptor of a code or data segment (not that of a system segment or gate).

• For the VERR instruction, the segment must be readable.

• For the VERW instruction, the segment must be a writable data segment.

• If the segment is not a conforming code segment, the segment’s DPL must be greater than or equal to (have less or the same privilege as) both the CPL and the segment selector's RPL.

  The validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS register, and the indicated access (read or write) is performed. The segment selector's value cannot result in a protection exception, enabling the software to anticipate possible segment access problems.

  This instruction’s operation is the same in non-64-bit modes and 64-bit mode. The operand size is fixed at 16 bits.

  
  

  Operation

  IF SRC(Offset)  (GDTR(Limit) or (LDTR(Limit)) THEN ZF  0; FI;

  Read segment descriptor;

  IF SegmentDescriptor(DescriptorType)  0 (* System segment *) or (SegmentDescriptor(Type)  conforming code segment)

  and (CPL  DPL) or (RPL  DPL) THEN

  ZF  0; ELSE

  IF ((Instruction  VERR) and (Segment readable))

  or ((Instruction  VERW) and (Segment writable)) THEN

  ZF  1;

  FI;

  FI;

  
  

  
  

  Flags Affected

  The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is set to 0.

  
  

  Protected Mode Exceptions

  The only exceptions generated for these instructions are those related to illegal addressing of the source operand.

  #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

  If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.

  #SS(0) If a memory operand effective address is outside the SS segment limit.

  #PF(fault-code) If a page fault occurs.

  #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

  #UD If the LOCK prefix is used.

  
  

  Real-Address Mode Exceptions

  #UD The VERR and VERW instructions are not recognized in real-address mode.

  If the LOCK prefix is used.

  
  

  Virtual-8086 Mode Exceptions

  #UD The VERR and VERW instructions are not recognized in virtual-8086 mode.

  If the LOCK prefix is used.

  
  

  Compatibility Mode Exceptions

  Same exceptions as in protected mode.

  
  

  64-Bit Mode Exceptions

  #SS(0) If a memory address referencing the SS segment is in a non-canonical form.

  #GP(0) If the memory address is in a non-canonical form.

  #PF(fault-code) If a page fault occurs.

  #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

  #UD If the LOCK prefix is used.

  
  

  VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extra

  ct Packed Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.256.66.0F3A.W0 19 /r ib VEXTRACTF128 xmm1/m128, ymm2, imm8	A	V/V	AVX	Extract 128 bits of packed floating-point values from ymm2 and store results in xmm1/m128.
  EVEX.256.66.0F3A.W0 19 /r ib VEXTRACTF32X4 xmm1/m128 {k1}{z}, ymm2, imm8	C	V/V	AVX512VL AVX512F	Extract 128 bits of packed single-precision floating- point values from ymm2 and store results in xmm1/m128 subject to writemask k1.
  EVEX.512.66.0F3A.W0 19 /r ib VEXTRACTF32x4 xmm1/m128 {k1}{z}, zmm2, imm8	C	V/V	AVX512F	Extract 128 bits of packed single-precision floating- point values from zmm2 and store results in xmm1/m128 subject to writemask k1.
  EVEX.256.66.0F3A.W1 19 /r ib VEXTRACTF64X2 xmm1/m128 {k1}{z}, ymm2, imm8	B	V/V	AVX512VL AVX512DQ	Extract 128 bits of packed double-precision floating-point values from ymm2 and store results in xmm1/m128 subject to writemask k1.
  EVEX.512.66.0F3A.W1 19 /r ib VEXTRACTF64X2 xmm1/m128 {k1}{z}, zmm2, imm8	B	V/V	AVX512DQ	Extract 128 bits of packed double-precision floating-point values from zmm2 and store results in xmm1/m128 subject to writemask k1.
  EVEX.512.66.0F3A.W0 1B /r ib VEXTRACTF32X8 ymm1/m256 {k1}{z}, zmm2, imm8	D	V/V	AVX512DQ	Extract 256 bits of packed single-precision floating- point values from zmm2 and store results in ymm1/m256 subject to writemask k1.
  EVEX.512.66.0F3A.W1 1B /r ib VEXTRACTF64x4 ymm1/m256 {k1}{z}, zmm2, imm8	C	V/V	AVX512F	Extract 256 bits of packed double-precision floating-point values from zmm2 and store results in ymm1/m256 subject to writemask k1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA
  B	Tuple2	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA
  C	Tuple4	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA
  D	Tuple8	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA

  Description

  VEXTRACTF128/VEXTRACTF32x4 and VEXTRACTF64x2 extract 128-bits of single-precision floating-point values from the source operand (the second operand) and store to the low 128-bit of the destination operand (the first operand). The 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or imm8[1:0] as the multiply factor. The destination may be either a vector register or an 128-bit memory location.

  VEXTRACTF32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the writemask.

  VEXTRACTF32x8 and VEXTRACTF64x4 extract 256-bits of double-precision floating-point values from the source operand (second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit data extraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply factor The destination may be either a vector register or a 256-bit memory location.

  VEXTRACTF64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the writemask.

  VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD. The high 6 bits of the immediate are ignored.

  If VEXTRACTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an #UD exception.

  
  

  
  

  Operation

  VEXTRACTF32x4 (EVEX encoded versions) when destination is a register

  VL = 256, 512 IF VL = 256

  CASE (imm8[0]) OF

  0: TMP_DEST[127:0]  SRC1[127:0]

  1: TMP_DEST[127:0]  SRC1[255:128] ESAC.

  FI;

  IF VL = 512

  CASE (imm8[1:0]) OF

  00: TMP_DEST[127:0]  SRC1[127:0]

  01: TMP_DEST[127:0]  SRC1[255:128]

  10: TMP_DEST[127:0]  SRC1[383:256]

  11: TMP_DEST[127:0]  SRC1[511:384] ESAC.

  FI;

  FOR j  0 TO 3

  i  j * 32

  IF k1[j] OR *no writemask*

  THEN DEST[i+31:i]  TMP_DEST[i+31:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE *zeroing-masking* ; zeroing-masking DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:128]  0

  
  

  VEXTRACTF32x4 (EVEX encoded versions) when destination is memory

  VL = 256, 512 IF VL = 256

  CASE (imm8[0]) OF

  0: TMP_DEST[127:0]  SRC1[127:0]

  1: TMP_DEST[127:0]  SRC1[255:128] ESAC.

  FI;

  IF VL = 512

  CASE (imm8[1:0]) OF

  00: TMP_DEST[127:0]  SRC1[127:0]

  01: TMP_DEST[127:0]  SRC1[255:128]

  10: TMP_DEST[127:0]  SRC1[383:256]

  11: TMP_DEST[127:0]  SRC1[511:384] ESAC.

  FI;

  
  

  FOR j  0 TO 3

  i  j * 32

  IF k1[j] OR *no writemask*

  THEN DEST[i+31:i]  TMP_DEST[i+31:i]

  ELSE *DEST[i+31:i] remains unchanged* ; merging-masking

  FI;

  
  

  
  

  ENDFOR

  
  

  VEXTRACTF64x2 (EVEX encoded versions) when destination is a register

  VL = 256, 512 IF VL = 256

  CASE (imm8[0]) OF

  0: TMP_DEST[127:0]  SRC1[127:0]

  1: TMP_DEST[127:0]  SRC1[255:128] ESAC.

  FI;

  IF VL = 512

  CASE (imm8[1:0]) OF

  00: TMP_DEST[127:0]  SRC1[127:0]

  01: TMP_DEST[127:0]  SRC1[255:128]

  10: TMP_DEST[127:0]  SRC1[383:256]

  11: TMP_DEST[127:0]  SRC1[511:384] ESAC.

  FI;

  
  

  FOR j  0 TO 1

  i  j * 64

  IF k1[j] OR *no writemask*

  THEN DEST[i+63:i]  TMP_DEST[i+63:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE *zeroing-masking* ; zeroing-masking DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:128]  0

  
  

  VEXTRACTF64x2 (EVEX encoded versions) when destination is memory

  VL = 256, 512 IF VL = 256

  CASE (imm8[0]) OF

  0: TMP_DEST[127:0]  SRC1[127:0]

  1: TMP_DEST[127:0]  SRC1[255:128] ESAC.

  FI;

  IF VL = 512

  CASE (imm8[1:0]) OF

  00: TMP_DEST[127:0]  SRC1[127:0]

  01: TMP_DEST[127:0]  SRC1[255:128]

  10: TMP_DEST[127:0]  SRC1[383:256]

  11: TMP_DEST[127:0]  SRC1[511:384] ESAC.

  FI;

  
  

  FOR j  0 TO 1

  i  j * 64

  IF k1[j] OR *no writemask*

  THEN DEST[i+63:i]  TMP_DEST[i+63:i]

  
  

  
  

  ELSE *DEST[i+63:i] remains unchanged* ; merging-masking

  FI;

  ENDFOR

  
  

  VEXTRACTF32x8 (EVEX.U1.512 encoded version) when destination is a register

  VL = 512

  CASE (imm8[0]) OF

  0: TMP_DEST[255:0]  SRC1[255:0]

  1: TMP_DEST[255:0]  SRC1[511:256] ESAC.

  
  

  FOR j  0 TO 7

  i  j * 32

  IF k1[j] OR *no writemask*

  THEN DEST[i+31:i]  TMP_DEST[i+31:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE *zeroing-masking* ; zeroing-masking DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:256]  0

  
  

  VEXTRACTF32x8 (EVEX.U1.512 encoded version) when destination is memory

  CASE (imm8[0]) OF

  0: TMP_DEST[255:0]  SRC1[255:0]

  1: TMP_DEST[255:0]  SRC1[511:256] ESAC.

  
  

  FOR j  0 TO 7

  i  j * 32

  IF k1[j] OR *no writemask*

  THEN DEST[i+31:i]  TMP_DEST[i+31:i]

  ELSE *DEST[i+31:i] remains unchanged* ; merging-masking

  FI;

  ENDFOR

  
  

  VEXTRACTF64x4 (EVEX.512 encoded version) when destination is a register

  VL = 512

  CASE (imm8[0]) OF

  0: TMP_DEST[255:0]  SRC1[255:0]

  1: TMP_DEST[255:0]  SRC1[511:256] ESAC.

  
  

  FOR j  0 TO 3

  i  j * 64

  IF k1[j] OR *no writemask*

  THEN DEST[i+63:i]  TMP_DEST[i+63:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE *zeroing-masking* ; zeroing-masking

  
  

  
  

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:256]  0

  
  

  VEXTRACTF64x4 (EVEX.512 encoded version) when destination is memory

  CASE (imm8[0]) OF

  0: TMP_DEST[255:0]  SRC1[255:0]

  1: TMP_DEST[255:0]  SRC1[511:256] ESAC.

  
  

  FOR j  0 TO 3

  i  j * 64

  IF k1[j] OR *no writemask*

  THEN DEST[i+63:i]  TMP_DEST[i+63:i]

  ELSE ; merging-masking

  *DEST[i+63:i] remains unchanged*

  FI;

  ENDFOR

  
  

  VEXTRACTF128 (memory destination form)

  CASE (imm8[0]) OF

  0: DEST[127:0] SRC1[127:0]

  1: DEST[127:0] SRC1[255:128] ESAC.

  
  

  VEXTRACTF128 (register destination form)

  CASE (imm8[0]) OF

  0: DEST[127:0] SRC1[127:0]

  1: DEST[127:0] SRC1[255:128] ESAC.

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VEXTRACTF32x4 m128 _mm512_extractf32x4_ps( m512 a, const int nidx);

  VEXTRACTF32x4 m128 _mm512_mask_extractf32x4_ps( m128 s, mmask8 k, m512 a, const int nidx); VEXTRACTF32x4 m128 _mm512_maskz_extractf32x4_ps( mmask8 k, m512 a, const int nidx); VEXTRACTF32x4 m128 _mm256_extractf32x4_ps( m256 a, const int nidx);

  VEXTRACTF32x4 m128 _mm256_mask_extractf32x4_ps( m128 s, mmask8 k, m256 a, const int nidx); VEXTRACTF32x4 m128 _mm256_maskz_extractf32x4_ps( mmask8 k, m256 a, const int nidx); VEXTRACTF32x8 m256 _mm512_extractf32x8_ps( m512 a, const int nidx);

  VEXTRACTF32x8 m256 _mm512_mask_extractf32x8_ps( m256 s, mmask8 k, m512 a, const int nidx); VEXTRACTF32x8 m256 _mm512_maskz_extractf32x8_ps( mmask8 k, m512 a, const int nidx); VEXTRACTF64x2 m128d _mm512_extractf64x2_pd( m512d a, const int nidx);

  VEXTRACTF64x2 m128d _mm512_mask_extractf64x2_pd( m128d s, mmask8 k, m512d a, const int nidx); VEXTRACTF64x2 m128d _mm512_maskz_extractf64x2_pd( mmask8 k, m512d a, const int nidx); VEXTRACTF64x2 m128d _mm256_extractf64x2_pd( m256d a, const int nidx);

  VEXTRACTF64x2 m128d _mm256_mask_extractf64x2_pd( m128d s, mmask8 k, m256d a, const int nidx); VEXTRACTF64x2 m128d _mm256_maskz_extractf64x2_pd( mmask8 k, m256d a, const int nidx); VEXTRACTF64x4 m256d _mm512_extractf64x4_pd( m512d a, const int nidx);

  VEXTRACTF64x4 m256d _mm512_mask_extractf64x4_pd( m256d s, mmask8 k, m512d a, const int nidx); VEXTRACTF64x4 m256d _mm512_maskz_extractf64x4_pd( mmask8 k, m512d a, const int nidx); VEXTRACTF128 m128 _mm256_extractf128_ps ( m256 a, int offset);

  
  

  
  

  VEXTRACTF128 m128d _mm256_extractf128_pd ( m256d a, int offset); VEXTRACTF128 m128i_mm256_extractf128_si256( m256i a, int offset);

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 6; EVEX-encoded instructions, see Exceptions Type E6NF.

  #UD IF VEX.L = 0.

  #UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

  
  

  VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract

  packed Integer Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.256.66.0F3A.W0 39 /r ib VEXTRACTI128 xmm1/m128, ymm2, imm8	A	V/V	AVX2	Extract 128 bits of integer data from ymm2 and store results in xmm1/m128.
  EVEX.256.66.0F3A.W0 39 /r ib VEXTRACTI32X4 xmm1/m128 {k1}{z}, ymm2, imm8	C	V/V	AVX512VL AVX512F	Extract 128 bits of double-word integer values from ymm2 and store results in xmm1/m128 subject to writemask k1.
  EVEX.512.66.0F3A.W0 39 /r ib VEXTRACTI32x4 xmm1/m128 {k1}{z}, zmm2, imm8	C	V/V	AVX512F	Extract 128 bits of double-word integer values from zmm2 and store results in xmm1/m128 subject to writemask k1.
  EVEX.256.66.0F3A.W1 39 /r ib VEXTRACTI64X2 xmm1/m128 {k1}{z}, ymm2, imm8	B	V/V	AVX512VL AVX512DQ	Extract 128 bits of quad-word integer values from ymm2 and store results in xmm1/m128 subject to writemask k1.
  EVEX.512.66.0F3A.W1 39 /r ib VEXTRACTI64X2 xmm1/m128 {k1}{z}, zmm2, imm8	B	V/V	AVX512DQ	Extract 128 bits of quad-word integer values from zmm2 and store results in xmm1/m128 subject to writemask k1.
  EVEX.512.66.0F3A.W0 3B /r ib VEXTRACTI32X8 ymm1/m256 {k1}{z}, zmm2, imm8	D	V/V	AVX512DQ	Extract 256 bits of double-word integer values from zmm2 and store results in ymm1/m256 subject to writemask k1.
  EVEX.512.66.0F3A.W1 3B /r ib VEXTRACTI64x4 ymm1/m256 {k1}{z}, zmm2, imm8	C	V/V	AVX512F	Extract 256 bits of quad-word integer values from zmm2 and store results in ymm1/m256 subject to writemask k1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA
  B	Tuple2	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA
  C	Tuple4	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA
  D	Tuple8	ModRM:r/m (w)	ModRM:reg (r)	Imm8	NA

  Description

  VEXTRACTI128/VEXTRACTI32x4 and VEXTRACTI64x2 extract 128-bits of doubleword integer values from the source operand (the second operand) and store to the low 128-bit of the destination operand (the first operand). The 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or imm8[1:0] as the multiply factor. The destination may be either a vector register or an 128-bit memory location.

  VEXTRACTI32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the writemask.

  VEXTRACTI64x2: The low 128-bit of the destination operand is updated at 64-bit granularity according to the writemask.

  VEXTRACTI32x8 and VEXTRACTI64x4 extract 256-bits of quadword integer values from the source operand (the second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit data extraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply factor The destination may be either a vector register or a 256-bit memory location.

  VEXTRACTI32x8: The low 256-bit of the destination operand is updated at 32-bit granularity according to the writemask.

  
  

  
  

  VEXTRACTI64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the writemask.

  VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD. The high 7 bits (6 bits in EVEX.512) of the immediate are ignored.

  If VEXTRACTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an #UD exception.

  
  

  Operation

  VEXTRACTI32x4 (EVEX encoded versions) when destination is a register

  VL = 256, 512 IF VL = 256

  CASE (imm8[0]) OF

  0: TMP_DEST[127:0]  SRC1[127:0]

  1: TMP_DEST[127:0]  SRC1[255:128] ESAC.

  FI;

  IF VL = 512

  CASE (imm8[1:0]) OF

  00: TMP_DEST[127:0]  SRC1[127:0]

  01: TMP_DEST[127:0]  SRC1[255:128]

  10: TMP_DEST[127:0]  SRC1[383:256]

  11: TMP_DEST[127:0]  SRC1[511:384] ESAC.

  FI;

  FOR j  0 TO 3

  i  j * 32

  IF k1[j] OR *no writemask*

  THEN DEST[i+31:i]  TMP_DEST[i+31:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE *zeroing-masking* ; zeroing-masking DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:128]  0

  
  

  VEXTRACTI32x4 (EVEX encoded versions) when destination is memory

  VL = 256, 512 IF VL = 256

  CASE (imm8[0]) OF

  0: TMP_DEST[127:0]  SRC1[127:0]

  1: TMP_DEST[127:0]  SRC1[255:128] ESAC.

  FI;

  IF VL = 512

  CASE (imm8[1:0]) OF

  00: TMP_DEST[127:0]  SRC1[127:0]

  01: TMP_DEST[127:0]  SRC1[255:128]

  10: TMP_DEST[127:0]  SRC1[383:256]

  11: TMP_DEST[127:0]  SRC1[511:384] ESAC.

  
  

  
  

  FI;

  
  

  FOR j  0 TO 3

  i  j * 32

  IF k1[j] OR *no writemask*

  THEN DEST[i+31:i]  TMP_DEST[i+31:i]

  ELSE *DEST[i+31:i] remains unchanged* ; merging-masking

  FI;

  ENDFOR

  
  

  VEXTRACTI64x2 (EVEX encoded versions) when destination is a register

  VL = 256, 512 IF VL = 256

  CASE (imm8[0]) OF

  0: TMP_DEST[127:0]  SRC1[127:0]

  1: TMP_DEST[127:0]  SRC1[255:128] ESAC.

  FI;

  IF VL = 512

  CASE (imm8[1:0]) OF

  00: TMP_DEST[127:0]  SRC1[127:0]

  01: TMP_DEST[127:0]  SRC1[255:128]

  10: TMP_DEST[127:0]  SRC1[383:256]

  11: TMP_DEST[127:0]  SRC1[511:384] ESAC.

  FI;

  
  

  FOR j  0 TO 1

  i  j * 64

  IF k1[j] OR *no writemask*

  THEN DEST[i+63:i]  TMP_DEST[i+63:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE *zeroing-masking* ; zeroing-masking DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:128]  0

  
  

  
  

  VEXTRACTI64x2 (EVEX encoded versions) when destination is memory

  VL = 256, 512 IF VL = 256

  CASE (imm8[0]) OF

  0: TMP_DEST[127:0]  SRC1[127:0]

  1: TMP_DEST[127:0]  SRC1[255:128] ESAC.

  FI;

  IF VL = 512

  CASE (imm8[1:0]) OF

  00: TMP_DEST[127:0]  SRC1[127:0]

  01: TMP_DEST[127:0]  SRC1[255:128]

  10: TMP_DEST[127:0]  SRC1[383:256]

  11: TMP_DEST[127:0]  SRC1[511:384] ESAC.

  FI;

  
  

  FOR j  0 TO 1

  i  j * 64

  IF k1[j] OR *no writemask*

  THEN DEST[i+63:i]  TMP_DEST[i+63:i]

  ELSE *DEST[i+63:i] remains unchanged* ; merging-masking

  FI;

  ENDFOR

  
  

  VEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is a register

  VL = 512

  CASE (imm8[0]) OF

  0: TMP_DEST[255:0]  SRC1[255:0]

  1: TMP_DEST[255:0]  SRC1[511:256] ESAC.

  
  

  FOR j  0 TO 7

  i  j * 32

  IF k1[j] OR *no writemask*

  THEN DEST[i+31:i]  TMP_DEST[i+31:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE *zeroing-masking* ; zeroing-masking DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:256]  0

  
  

  
  

  VEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is memory

  CASE (imm8[0]) OF

  0: TMP_DEST[255:0]  SRC1[255:0]

  1: TMP_DEST[255:0]  SRC1[511:256] ESAC.

  
  

  FOR j  0 TO 7

  i  j * 32

  IF k1[j] OR *no writemask*

  THEN DEST[i+31:i]  TMP_DEST[i+31:i]

  ELSE *DEST[i+31:i] remains unchanged* ; merging-masking

  FI;

  ENDFOR

  
  

  VEXTRACTI64x4 (EVEX.512 encoded version) when destination is a register

  VL = 512

  CASE (imm8[0]) OF

  0: TMP_DEST[255:0]  SRC1[255:0]

  1: TMP_DEST[255:0]  SRC1[511:256] ESAC.

  
  

  FOR j  0 TO 3

  i  j * 64

  IF k1[j] OR *no writemask*

  THEN DEST[i+63:i]  TMP_DEST[i+63:i] ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE *zeroing-masking* ; zeroing-masking DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:256]  0

  
  

  VEXTRACTI64x4 (EVEX.512 encoded version) when destination is memory

  CASE (imm8[0]) OF

  0: TMP_DEST[255:0]  SRC1[255:0]

  1: TMP_DEST[255:0]  SRC1[511:256] ESAC.

  FOR j  0 TO 3

  i  j * 64

  IF k1[j] OR *no writemask*

  THEN DEST[i+63:i]  TMP_DEST[i+63:i]

  ELSE *DEST[i+63:i] remains unchanged* ; merging-masking

  FI;

  ENDFOR

  
  

  
  

  VEXTRACTI128 (memory destination form)

  CASE (imm8[0]) OF

  0: DEST[127:0] SRC1[127:0]

  1: DEST[127:0] SRC1[255:128] ESAC.

  
  

  VEXTRACTI128 (register destination form)

  CASE (imm8[0]) OF

  0: DEST[127:0] SRC1[127:0]

  1: DEST[127:0] SRC1[255:128] ESAC.

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VEXTRACTI32x4 m128i _mm512_extracti32x4_epi32( m512i a, const int nidx);

  VEXTRACTI32x4 m128i _mm512_mask_extracti32x4_epi32( m128i s, mmask8 k, m512i a, const int nidx); VEXTRACTI32x4 m128i _mm512_maskz_extracti32x4_epi32( mmask8 k, m512i a, const int nidx); VEXTRACTI32x4 m128i _mm256_extracti32x4_epi32( m256i a, const int nidx);

  VEXTRACTI32x4 m128i _mm256_mask_extracti32x4_epi32( m128i s, mmask8 k, m256i a, const int nidx); VEXTRACTI32x4 m128i _mm256_maskz_extracti32x4_epi32( mmask8 k, m256i a, const int nidx); VEXTRACTI32x8 m256i _mm512_extracti32x8_epi32( m512i a, const int nidx);

  VEXTRACTI32x8 m256i _mm512_mask_extracti32x8_epi32( m256i s, mmask8 k, m512i a, const int nidx); VEXTRACTI32x8 m256i _mm512_maskz_extracti32x8_epi32( mmask8 k, m512i a, const int nidx); VEXTRACTI64x2 m128i _mm512_extracti64x2_epi64( m512i a, const int nidx);

  VEXTRACTI64x2 m128i _mm512_mask_extracti64x2_epi64( m128i s, mmask8 k, m512i a, const int nidx); VEXTRACTI64x2 m128i _mm512_maskz_extracti64x2_epi64( mmask8 k, m512i a, const int nidx); VEXTRACTI64x2 m128i _mm256_extracti64x2_epi64( m256i a, const int nidx);

  VEXTRACTI64x2 m128i _mm256_mask_extracti64x2_epi64( m128i s, mmask8 k, m256i a, const int nidx); VEXTRACTI64x2 m128i _mm256_maskz_extracti64x2_epi64( mmask8 k, m256i a, const int nidx); VEXTRACTI64x4 m256i _mm512_extracti64x4_epi64( m512i a, const int nidx);

  VEXTRACTI64x4 m256i _mm512_mask_extracti64x4_epi64( m256i s, mmask8 k, m512i a, const int nidx); VEXTRACTI64x4 m256i _mm512_maskz_extracti64x4_epi64( mmask8 k, m512i a, const int nidx); VEXTRACTI128 m128i _mm256_extracti128_si256( m256i a, int offset);

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 6; EVEX-encoded instructions, see Exceptions Type E6NF.

  #UD IF VEX.L = 0.

  #UD If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

  
  

  VFIXUPIMMPD—Fix Up Special Packed Float64 Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.NDS.128.66.0F3A.W1 54 /r ib VFIXUPIMMPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst, imm8	A	V/V	AVX512VL AVX512F	Fix up special numbers in float64 vector xmm1, float64 vector xmm2 and int64 vector xmm3/m128/m64bcst and store the result in xmm1, under writemask.
  EVEX.NDS.256.66.0F3A.W1 54 /r ib VFIXUPIMMPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst, imm8	A	V/V	AVX512VL AVX512F	Fix up special numbers in float64 vector ymm1, float64 vector ymm2 and int64 vector ymm3/m256/m64bcst and store the result in ymm1, under writemask.
  EVEX.NDS.512.66.0F3A.W1 54 /r ib VFIXUPIMMPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{sae}, imm8	A	V/V	AVX512F	Fix up elements of float64 vector in zmm2 using int64 vector table in zmm3/m512/m64bcst, combine with preserved elements from zmm1, and store the result in zmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Full	ModRM:reg (r, w)	EVEX.vvvv	ModRM:r/m (r)	Imm8

  Description

  Perform fix-up of quad-word elements encoded in double-precision floating-point format in the first source operand (the second operand) using a 32-bit, two-level look-up table specified in the corresponding quadword element of the second source operand (the third operand) with exception reporting specifier imm8. The elements that are fixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table response action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from the first source operand and the preserved element in the first operand are combined as the final results in the destination operand (the first operand).

  The destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64- bit memory location.

  The two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the input data encoding into 8 token types. A response table is defined for each token type that converts the input encoding in the first source operand with one of 16 response actions.

  This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor- rect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the correct value (i.e. INF when the input is 0).

  If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and do not trigger any fixup nor fault reporting.

  Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).

  MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8 bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.

  This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1 are computed and stored into zmm1. Elements in the destination with the corresponding bit clear in k1 retain their previous values or are set to 0.

  
  

  
  

  Operation

  enum TOKEN_TYPE

  {

  QNAN_TOKEN  0,

  SNAN_TOKEN  1,

  ZERO_VALUE_TOKEN  2,

  POS_ONE_VALUE_TOKEN  3,

  NEG_INF_TOKEN  4,

  POS_INF_TOKEN  5,

  NEG_VALUE_TOKEN  6,

  POS_VALUE_TOKEN  7

  }

  
  

  FIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){

  tsrc[63:0]  ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0] CASE(tsrc[63:0] of TOKEN_TYPE) {

  QNAN_TOKEN: j  0; SNAN_TOKEN: j  1; ZERO_VALUE_TOKEN: j  2; POS_ONE_VALUE_TOKEN: j  3; NEG_INF_TOKEN: j  4; POS_INF_TOKEN: j  5; NEG_VALUE_TOKEN: j  6; POS_VALUE_TOKEN: j  7;

  } ; end source special CASE(tsrc…)

  
  

  ; The required response from src3 table is extracted token_response[3:0] = tbl3[3+4*j:4*j];

  
  

  CASE(token_response[3:0]) {

  0000: dest[63:0]  dest[63:0]; ; preserve content of DEST

  0001: dest[63:0]  tsrc[63:0]; ; pass through src1 normal input value, denormal as zero 0010: dest[63:0]  QNaN(tsrc[63:0]);

  0011: dest[63:0]  QNAN_Indefinite; 0100: dest[63:0]  -INF;

  0101: dest[63:0]  +INF;

  0110: dest[63:0]  tsrc.sign? –INF : +INF; 0111: dest[63:0]  -0;

  1000: dest[63:0]  +0;

  1001: dest[63:0]  -1;

  1010: dest[63:0]  +1;

  1011: dest[63:0]  ½;

  1100: dest[63:0]  90.0;

  1101: dest[63:0]  PI/2;

  1110: dest[63:0]  MAX_FLOAT;

  1111: dest[63:0]  -MAX_FLOAT;

  } ; end of token_response CASE

  
  

  
  

  ; The required fault reporting from imm8 is extracted

  ; TOKENs are mutually exclusive and TOKENs priority defines the order.

  ; Multiple faults related to a single token can occur simultaneously.

  IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE; IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;

  IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE; IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE; IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;

  IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;

  IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE; IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;

  ; end fault reporting return dest[63:0];

  } ; end of FIXUPIMM_DP()

  
  

  VFIXUPIMMPD

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN

  DEST[i+63:i]  FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[63:0], imm8 [7:0]) ELSE

  DEST[i+63:i]  FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[i+63:i], imm8 [7:0])

  FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE DEST[i+63:i]  0 ; zeroing-masking

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  

  Immediate Control Description:

  
  

  7

  6

  5

  4

  3

  2

  1

  0

  
  

  + INF 	#IE
  - VE 	#IE
  - INF 	#IE
  SNaN 	#IE
  ONE 	#IE
  ONE 	#ZE
  ZERO 	#IE
  ZERO 	#ZE

  
  

  Figure 5-9. VFIXUPIMMPD Immediate Control Description

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFIXUPIMMPD m512d _mm512_fixupimm_pd( m512d a, m512i tbl, int imm);

  VFIXUPIMMPD m512d _mm512_mask_fixupimm_pd( m512d s, mmask8 k, m512d a, m512i tbl, int imm); VFIXUPIMMPD m512d _mm512_maskz_fixupimm_pd( mmask8 k, m512d a, m512i tbl, int imm); VFIXUPIMMPD m512d _mm512_fixupimm_round_pd( m512d a, m512i tbl, int imm, int sae);

  VFIXUPIMMPD m512d _mm512_mask_fixupimm_round_pd( m512d s, mmask8 k, m512d a, m512i tbl, int imm, int sae); VFIXUPIMMPD m512d _mm512_maskz_fixupimm_round_pd( mmask8 k, m512d a, m512i tbl, int imm, int sae); VFIXUPIMMPD m256d _mm256_fixupimm_pd( m256d a, m256i tbl, int imm);

  VFIXUPIMMPD m256d _mm256_mask_fixupimm_pd( m256d s, mmask8 k, m256d a, m256i tbl, int imm); VFIXUPIMMPD m256d _mm256_maskz_fixupimm_pd( mmask8 k, m256d a, m256i tbl, int imm); VFIXUPIMMPD m128d _mm_fixupimm_pd( m128d a, m128i tbl, int imm);

  VFIXUPIMMPD m128d _mm_mask_fixupimm_pd( m128d s, mmask8 k, m128d a, m128i tbl, int imm); VFIXUPIMMPD m128d _mm_maskz_fixupimm_pd( mmask8 k, m128d a, m128i tbl, int imm);

  
  

  SIMD Floating-Point Exceptions

  Zero, Invalid

  
  

  Other Exceptions

  See Exceptions Type E2.

  
  

  VFIXUPIMMPS—Fix Up Special Packed Float32 Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.NDS.128.66.0F3A.W0 54 /r VFIXUPIMMPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst, imm8	A	V/V	AVX512VL AVX512F	Fix up special numbers in float32 vector xmm1, float32 vector xmm2 and int32 vector xmm3/m128/m32bcst and store the result in xmm1, under writemask.
  EVEX.NDS.256.66.0F3A.W0 54 /r VFIXUPIMMPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst, imm8	A	V/V	AVX512VL AVX512F	Fix up special numbers in float32 vector ymm1, float32 vector ymm2 and int32 vector ymm3/m256/m32bcst and store the result in ymm1, under writemask.
  EVEX.NDS.512.66.0F3A.W0 54 /r ib VFIXUPIMMPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{sae}, imm8	A	V/V	AVX512F	Fix up elements of float32 vector in zmm2 using int32 vector table in zmm3/m512/m32bcst, combine with preserved elements from zmm1, and store the result in zmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Full	ModRM:reg (r, w)	EVEX.vvvv	ModRM:r/m (r)	Imm8

  Description

  Perform fix-up of doubleword elements encoded in single-precision floating-point format in the first source operand (the second operand) using a 32-bit, two-level look-up table specified in the corresponding doubleword element of the second source operand (the third operand) with exception reporting specifier imm8. The elements that are fixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table response action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from the first source operand and the preserved element in the first operand are combined as the final results in the destination operand (the first operand).

  The destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64- bit memory location.

  The two-level look-up table perform a fix-up of each SP FP input data in the first source operand by decoding the input data encoding into 8 token types. A response table is defined for each token type that converts the input encoding in the first source operand with one of 16 response actions.

  This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor- rect result. To deal with this, VFIXUPIMMPS can be used after the N-R reciprocal sequence to set the result to the correct value (i.e. INF when the input is 0).

  If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and do not trigger any fixup nor fault reporting.

  Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below). MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).

  MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8 bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.

  
  

  
  

  Operation

  enum TOKEN_TYPE

  {

  QNAN_TOKEN  0,

  SNAN_TOKEN  1,

  ZERO_VALUE_TOKEN  2,

  POS_ONE_VALUE_TOKEN  3,

  NEG_INF_TOKEN  4,

  POS_INF_TOKEN  5,

  NEG_VALUE_TOKEN  6,

  POS_VALUE_TOKEN  7

  }

  
  

  FIXUPIMM_SP ( dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){

  tsrc[31:0]  ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0] CASE(tsrc[31:0] of TOKEN_TYPE) {

  QNAN_TOKEN: j  0; SNAN_TOKEN: j  1; ZERO_VALUE_TOKEN: j  2; POS_ONE_VALUE_TOKEN: j  3; NEG_INF_TOKEN: j  4; POS_INF_TOKEN: j  5; NEG_VALUE_TOKEN: j  6; POS_VALUE_TOKEN: j  7;

  } ; end source special CASE(tsrc…)

  
  

  ; The required response from src3 table is extracted token_response[3:0] = tbl3[3+4*j:4*j];

  
  

  CASE(token_response[3:0]) {

  0000: dest[31:0]  dest[31:0]; ; preserve content of DEST

  0001: dest[31:0]  tsrc[31:0]; ; pass through src1 normal input value, denormal as zero 0010: dest[31:0]  QNaN(tsrc[31:0]);

  0011: dest[31:0]  QNAN_Indefinite; 0100: dest[31:0]  -INF;

  0101: dest[31:0]  +INF;

  0110: dest[31:0]  tsrc.sign? –INF : +INF; 0111: dest[31:0]  -0;

  1000: dest[31:0]  +0;

  1001: dest[31:0]  -1;

  1010: dest[31:0]  +1;

  1011: dest[31:0]  ½;

  1100: dest[31:0]  90.0;

  1101: dest[31:0]  PI/2;

  1110: dest[31:0]  MAX_FLOAT;

  1111: dest[31:0]  -MAX_FLOAT;

  } ; end of token_response CASE

  
  

  
  

  ; The required fault reporting from imm8 is extracted

  ; TOKENs are mutually exclusive and TOKENs priority defines the order.

  ; Multiple faults related to a single token can occur simultaneously.

  IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE; IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;

  IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE; IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE; IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;

  IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;

  IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE; IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;

  ; end fault reporting return dest[31:0];

  } ; end of FIXUPIMM_SP()

  
  

  VFIXUPIMMPS (EVEX)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) AND (SRC2 *is memory*) THEN

  DEST[i+31:i]  FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[31:0], imm8 [7:0]) ELSE

  DEST[i+31:i]  FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[i+31:i], imm8 [7:0])

  FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE DEST[i+31:i]  0 ; zeroing-masking

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  

  Immediate Control Description:

  
  

  7

  6

  5

  4

  3

  2

  1

  0

  
  

  + INF 	#IE
  - VE 	#IE
  - INF 	#IE
  SNaN 	#IE
  ONE 	#IE
  ONE 	#ZE
  ZERO 	#IE
  ZERO 	#ZE

  
  

  Figure 5-10. VFIXUPIMMPS Immediate Control Description

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFIXUPIMMPS m512 _mm512_fixupimm_ps( m512 a, m512i tbl, int imm);

  VFIXUPIMMPS m512 _mm512_mask_fixupimm_ps( m512 s, mmask16 k, m512 a, m512i tbl, int imm); VFIXUPIMMPS m512 _mm512_maskz_fixupimm_ps( mmask16 k, m512 a, m512i tbl, int imm); VFIXUPIMMPS m512 _mm512_fixupimm_round_ps( m512 a, m512i tbl, int imm, int sae);

  VFIXUPIMMPS m512 _mm512_mask_fixupimm_round_ps( m512 s, mmask16 k, m512 a, m512i tbl, int imm, int sae); VFIXUPIMMPS m512 _mm512_maskz_fixupimm_round_ps( mmask16 k, m512 a, m512i tbl, int imm, int sae); VFIXUPIMMPS m256 _mm256_fixupimm_ps( m256 a, m256i tbl, int imm);

  VFIXUPIMMPS m256 _mm256_mask_fixupimm_ps( m256 s, mmask8 k, m256 a, m256i tbl, int imm); VFIXUPIMMPS m256 _mm256_maskz_fixupimm_ps( mmask8 k, m256 a, m256i tbl, int imm); VFIXUPIMMPS m128 _mm_fixupimm_ps( m128 a, m128i tbl, int imm);

  VFIXUPIMMPS m128 _mm_mask_fixupimm_ps( m128 s, mmask8 k, m128 a, m128i tbl, int imm); VFIXUPIMMPS m128 _mm_maskz_fixupimm_ps( mmask8 k, m128 a, m128i tbl, int imm);

  
  

  SIMD Floating-Point Exceptions

  Zero, Invalid

  
  

  Other Exceptions

  See Exceptions Type E2.

  
  

  VFIXUPIMMSD—Fix Up Special Scalar Float64 Value

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.NDS.LIG.66.0F3A.W1 55 /r ib VFIXUPIMMSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8	A	V/V	AVX512F	Fix up a float64 number in the low quadword element of xmm2 using scalar int32 table in xmm3/m64 and store the result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv	ModRM:r/m (r)	Imm8

  Description

  Perform a fix-up of the low quadword element encoded in double-precision floating-point format in the first source operand (the second operand) using a 32-bit, two-level look-up table specified in the low quadword element of the second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-up is selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action of 0000b preserves the corresponding element of the first operand. The fixed-up element from the first source operand or the preserved element in the first operand becomes the low quadword element of the destination operand (the first operand). Bits 127:64 of the destination operand is copied from the corresponding bits of the first source operand. The destination and first source operands are XMM registers. The second source operand can be a XMM register or a 64- bit memory location.

  The two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the input data encoding into 8 token types. A response table is defined for each token type that converts the input encoding in the first source operand with one of 16 response actions.

  This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor- rect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the correct value (i.e. INF when the input is 0).

  If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and do not trigger any fixup nor fault reporting.

  Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below). MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).

  MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8 bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.

  
  

  Operation

  enum TOKEN_TYPE

  {

  QNAN_TOKEN  0,

  SNAN_TOKEN  1,

  ZERO_VALUE_TOKEN  2,

  POS_ONE_VALUE_TOKEN  3,

  NEG_INF_TOKEN  4,

  POS_INF_TOKEN  5,

  NEG_VALUE_TOKEN  6,

  POS_VALUE_TOKEN  7

  }

  
  

  FIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){

  tsrc[63:0]  ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0] CASE(tsrc[63:0] of TOKEN_TYPE) {

  QNAN_TOKEN: j  0; SNAN_TOKEN: j  1; ZERO_VALUE_TOKEN: j  2; POS_ONE_VALUE_TOKEN: j  3; NEG_INF_TOKEN: j  4; POS_INF_TOKEN: j  5; NEG_VALUE_TOKEN: j  6; POS_VALUE_TOKEN: j  7;

  } ; end source special CASE(tsrc…)

  
  

  ; The required response from src3 table is extracted token_response[3:0] = tbl3[3+4*j:4*j];

  
  

  CASE(token_response[3:0]) {

  0000: dest[63:0]  dest[63:0] ; preserve content of DEST

  0001: dest[63:0]  tsrc[63:0]; ; pass through src1 normal input value, denormal as zero 0010: dest[63:0]  QNaN(tsrc[63:0]);

  0011: dest[63:0]  QNAN_Indefinite; 0100:dest[63:0]  -INF;

  0101: dest[63:0]  +INF;

  0110: dest[63:0]  tsrc.sign? –INF : +INF; 0111: dest[63:0]  -0;

  1000: dest[63:0]  +0;

  1001: dest[63:0]  -1;

  1010: dest[63:0]  +1;

  1011: dest[63:0]  ½;

  1100: dest[63:0]  90.0;

  1101: dest[63:0]  PI/2;

  1110: dest[63:0]  MAX_FLOAT;

  1111: dest[63:0]  -MAX_FLOAT;

  } ; end of token_response CASE

  
  

  ; The required fault reporting from imm8 is extracted

  ; TOKENs are mutually exclusive and TOKENs priority defines the order.

  ; Multiple faults related to a single token can occur simultaneously.

  IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE; IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;

  IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE; IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE; IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;

  IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;

  IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE; IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;

  ; end fault reporting return dest[63:0];

  } ; end of FIXUPIMM_DP()

  
  

  
  

  VFIXUPIMMSD (EVEX encoded version)

  IF k1[0] OR *no writemask*

  THEN DEST[63:0]  FIXUPIMM_DP(DEST[63:0], SRC1[63:0], SRC2[63:0], imm8 [7:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE DEST[63:0]  0 ; zeroing-masking

  FI

  FI;

  DEST[127:64]  SRC1[127:64] DEST[MAXVL-1:128]  0

  
  

  

  Immediate Control Description:

  
  

  7

  6

  5

  4

  3

  2

  1

  0

  
  

  + INF 	#IE
  - VE 	#IE
  - INF 	#IE
  SNaN 	#IE
  ONE 	#IE
  ONE 	#ZE
  ZERO 	#IE
  ZERO 	#ZE

  
  

  Figure 5-11. VFIXUPIMMSD Immediate Control Description

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFIXUPIMMSD m128d _mm_fixupimm_sd( m128d a, m128i tbl, int imm);

  VFIXUPIMMSD m128d _mm_mask_fixupimm_sd( m128d s, mmask8 k, m128d a, m128i tbl, int imm); VFIXUPIMMSD m128d _mm_maskz_fixupimm_sd( mmask8 k, m128d a, m128i tbl, int imm); VFIXUPIMMSD m128d _mm_fixupimm_round_sd( m128d a, m128i tbl, int imm, int sae);

  VFIXUPIMMSD m128d _mm_mask_fixupimm_round_sd( m128d s, mmask8 k, m128d a, m128i tbl, int imm, int sae); VFIXUPIMMSD m128d _mm_maskz_fixupimm_round_sd( mmask8 k, m128d a, m128i tbl, int imm, int sae);

  
  

  SIMD Floating-Point Exceptions

  Zero, Invalid

  
  

  Other Exceptions

  See Exceptions Type E3.

  
  

  VFIXUPIMMSS—Fix Up Special Scalar Float32 Value

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.NDS.LIG.66.0F3A.W0 55 /r ib VFIXUPIMMSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae}, imm8	A	V/V	AVX512F	Fix up a float32 number in the low doubleword element in xmm2 using scalar int32 table in xmm3/m32 and store the result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv	ModRM:r/m (r)	Imm8

  Description

  Perform a fix-up of the low doubleword element encoded in single-precision floating-point format in the first source operand (the second operand) using a 32-bit, two-level look-up table specified in the low doubleword element of the second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed- up is selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action of 0000b preserves the corresponding element of the first operand. The fixed-up element from the first source operand or the preserved element in the first operand becomes the low doubleword element of the destination operand (the first operand) Bits 127:32 of the destination operand is copied from the corresponding bits of the first source operand. The destination and first source operands are XMM registers. The second source operand can be a XMM register or a 32-bit memory location.

  The two-level look-up table perform a fix-up of each SP FP input data in the first source operand by decoding the input data encoding into 8 token types. A response table is defined for each token type that converts the input encoding in the first source operand with one of 16 response actions.

  This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor- rect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the correct value (i.e. INF when the input is 0).

  If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and do not trigger any fixup nor fault reporting.

  Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below). MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).

  MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8 bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.

  
  

  Operation

  enum TOKEN_TYPE

  {

  QNAN_TOKEN  0,

  SNAN_TOKEN  1,

  ZERO_VALUE_TOKEN  2,

  POS_ONE_VALUE_TOKEN  3,

  NEG_INF_TOKEN  4,

  POS_INF_TOKEN  5,

  NEG_VALUE_TOKEN  6,

  POS_VALUE_TOKEN  7

  }

  
  

  FIXUPIMM_SP (dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){

  tsrc[31:0]  ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0] CASE(tsrc[63:0] of TOKEN_TYPE) {

  QNAN_TOKEN: j  0; SNAN_TOKEN: j  1; ZERO_VALUE_TOKEN: j  2; POS_ONE_VALUE_TOKEN: j  3; NEG_INF_TOKEN: j  4; POS_INF_TOKEN: j  5; NEG_VALUE_TOKEN: j  6; POS_VALUE_TOKEN: j = 7;

  } ; end source special CASE(tsrc…)

  
  

  ; The required response from src3 table is extracted token_response[3:0] = tbl3[3+4*j:4*j];

  
  

  CASE(token_response[3:0]) {

  0000: dest[31:0]  dest[31:0]; ; preserve content of DEST

  0001: dest[31:0]  tsrc[31:0]; ; pass through src1 normal input value, denormal as zero 0010: dest[31:0]  QNaN(tsrc[31:0]);

  0011: dest[31:0]  QNAN_Indefinite; 0100: dest[31:0]  -INF;

  0101: dest[31:0]  +INF;

  0110: dest[31:0]  tsrc.sign? –INF : +INF; 0111: dest[31:0]  -0;

  1000: dest[31:0]  +0;

  1001: dest[31:0]  -1;

  1010: dest[31:0]  +1;

  1011: dest[31:0]  ½;

  1100: dest[31:0]  90.0;

  1101: dest[31:0]  PI/2;

  1110: dest[31:0]  MAX_FLOAT;

  1111: dest[31:0]  -MAX_FLOAT;

  } ; end of token_response CASE

  
  

  ; The required fault reporting from imm8 is extracted

  ; TOKENs are mutually exclusive and TOKENs priority defines the order.

  ; Multiple faults related to a single token can occur simultaneously.

  IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE; IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;

  IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE; IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE; IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;

  IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;

  IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE; IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;

  ; end fault reporting return dest[31:0];

  } ; end of FIXUPIMM_SP()

  
  

  
  

  VFIXUPIMMSS (EVEX encoded version)

  IF k1[0] OR *no writemask*

  THEN DEST[31:0]  FIXUPIMM_SP(DEST[31:0], SRC1[31:0], SRC2[31:0], imm8 [7:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE DEST[31:0]  0 ; zeroing-masking

  FI

  FI;

  DEST[127:32]  SRC1[127:32] DEST[MAXVL-1:128]  0

  
  

  

  Immediate Control Description:

  
  

  7

  6

  5

  4

  3

  2

  1

  0

  
  

  + INF 	#IE
  - VE 	#IE
  - INF 	#IE
  SNaN 	#IE
  ONE 	#IE
  ONE 	#ZE
  ZERO 	#IE
  ZERO 	#ZE

  
  

  Figure 5-12. VFIXUPIMMSS Immediate Control Description

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFIXUPIMMSS m128 _mm_fixupimm_ss( m128 a, m128i tbl, int imm);

  VFIXUPIMMSS m128 _mm_mask_fixupimm_ss( m128 s, mmask8 k, m128 a, m128i tbl, int imm); VFIXUPIMMSS m128 _mm_maskz_fixupimm_ss( mmask8 k, m128 a, m128i tbl, int imm); VFIXUPIMMSS m128 _mm_fixupimm_round_ss( m128 a, m128i tbl, int imm, int sae);

  VFIXUPIMMSS m128 _mm_mask_fixupimm_round_ss( m128 s, mmask8 k, m128 a, m128i tbl, int imm, int sae); VFIXUPIMMSS m128 _mm_maskz_fixupimm_round_ss( mmask8 k, m128 a, m128i tbl, int imm, int sae);

  
  

  SIMD Floating-Point Exceptions

  Zero, Invalid

  
  

  Other Exceptions

  See Exceptions Type E3.

  
  

  VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double- Precision Floating-Point Values

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.NDS.128.66.0F38.W1 98 /r VFMADD132PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, add to xmm2 and put result in xmm1.
  VEX.NDS.128.66.0F38.W1 A8 /r VFMADD213PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm2, add to xmm3/mem and put result in xmm1.
  VEX.NDS.128.66.0F38.W1 B8 /r VFMADD231PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, add to xmm1 and put result in xmm1.
  VEX.NDS.256.66.0F38.W1 98 /r VFMADD132PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, add to ymm2 and put result in ymm1.
  VEX.NDS.256.66.0F38.W1 A8 /r VFMADD213PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm2, add to ymm3/mem and put result in ymm1.
  VEX.NDS.256.66.0F38.W1 B8 /r VFMADD231PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, add to ymm1 and put result in ymm1.
  EVEX.NDS.128.66.0F38.W1 98 /r VFMADD132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	A	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, add to xmm2 and put result in xmm1.
  EVEX.NDS.128.66.0F38.W1 A8 /r VFMADD213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm2, add to xmm3/m128/m64bcst and put result in xmm1.
  EVEX.NDS.128.66.0F38.W1 B8 /r VFMADD231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, add to xmm1 and put result in xmm1.
  EVEX.NDS.256.66.0F38.W1 98 /r VFMADD132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, add to ymm2 and put result in ymm1.
  EVEX.NDS.256.66.0F38.W1 A8 /r VFMADD213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm2, add to ymm3/m256/m64bcst and put result in ymm1.
  EVEX.NDS.256.66.0F38.W1 B8 /r VFMADD231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, add to ymm1 and put result in ymm1.
  EVEX.NDS.512.66.0F38.W1 98 /r VFMADD132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, add to zmm2 and put result in zmm1.
  EVEX.NDS.512.66.0F38.W1 A8 /r VFMADD213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm2, add to zmm3/m512/m64bcst and put result in zmm1.
  EVEX.NDS.512.66.0F38.W1 B8 /r VFMADD231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, add to zmm1 and put result in zmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  Performs a set of SIMD multiply-add computation on packed double-precision floating-point values using three source operands and writes the multiply-add results in the destination operand. The destination operand is also the first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD register or a memory location.

  VFMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source operand to the two, four or eight packed double-precision floating-point values in the third source operand, adds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the second source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  VFMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source operand to the two, four or eight packed double-precision floating-point values in the first source operand, adds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the third source operand, performs rounding and stores the resulting two, four or eight packed double- precision floating-point values to the destination operand (first source operand).

  VFMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source to the two, four or eight packed double-precision floating-point values in the third source operand, adds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in reg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is conditionally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  
  

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFMADD132PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] + SRC2[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMADD213PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] + SRC3[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMADD231PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] + DEST[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMADDxxxPD m512d _mm512_fmadd_pd( m512d a, m512d b, m512d c); VFMADDxxxPD m512d _mm512_fmadd_round_pd( m512d a, m512d b, m512d c, int r);

  VFMADDxxxPD m512d _mm512_mask_fmadd_pd( m512d a, mmask8 k, m512d b, m512d c); VFMADDxxxPD m512d _mm512_maskz_fmadd_pd( mmask8 k, m512d a, m512d b, m512d c); VFMADDxxxPD m512d _mm512_mask3_fmadd_pd( m512d a, m512d b, m512d c, mmask8 k); VFMADDxxxPD m512d _mm512_mask_fmadd_round_pd( m512d a, mmask8 k, m512d b, m512d c, int r); VFMADDxxxPD m512d _mm512_maskz_fmadd_round_pd( mmask8 k, m512d a, m512d b, m512d c, int r); VFMADDxxxPD m512d _mm512_mask3_fmadd_round_pd( m512d a, m512d b, m512d c, mmask8 k, int r); VFMADDxxxPD m256d _mm256_mask_fmadd_pd( m256d a, mmask8 k, m256d b, m256d c); VFMADDxxxPD m256d _mm256_maskz_fmadd_pd( mmask8 k, m256d a, m256d b, m256d c); VFMADDxxxPD m256d _mm256_mask3_fmadd_pd( m256d a, m256d b, m256d c, mmask8 k); VFMADDxxxPD m128d _mm_mask_fmadd_pd( m128d a, mmask8 k, m128d b, m128d c);

  VFMADDxxxPD m128d _mm_maskz_fmadd_pd( mmask8 k, m128d a, m128d b, m128d c); VFMADDxxxPD m128d _mm_mask3_fmadd_pd( m128d a, m128d b, m128d c, mmask8 k); VFMADDxxxPD m128d _mm_fmadd_pd ( m128d a, m128d b, m128d c);

  VFMADDxxxPD m256d _mm256_fmadd_pd ( m256d a, m256d b, m256d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single- Precision Floating-Point Values

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.NDS.128.66.0F38.W0 98 /r VFMADD132PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, add to xmm2 and put result in xmm1.
  VEX.NDS.128.66.0F38.W0 A8 /r VFMADD213PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm2, add to xmm3/mem and put result in xmm1.
  VEX.NDS.128.66.0F38.W0 B8 /r VFMADD231PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, add to xmm1 and put result in xmm1.
  VEX.NDS.256.66.0F38.W0 98 /r VFMADD132PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, add to ymm2 and put result in ymm1.
  VEX.NDS.256.66.0F38.W0 A8 /r VFMADD213PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm2, add to ymm3/mem and put result in ymm1.
  VEX.NDS.256.66.0F38.0 B8 /r VFMADD231PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, add to ymm1 and put result in ymm1.
  EVEX.NDS.128.66.0F38.W0 98 /r VFMADD132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, add to xmm2 and put result in xmm1.
  EVEX.NDS.128.66.0F38.W0 A8 /r VFMADD213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm2, add to xmm3/m128/m32bcst and put result in xmm1.
  EVEX.NDS.128.66.0F38.W0 B8 /r VFMADD231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, add to xmm1 and put result in xmm1.
  EVEX.NDS.256.66.0F38.W0 98 /r VFMADD132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, add to ymm2 and put result in ymm1.
  EVEX.NDS.256.66.0F38.W0 A8 /r VFMADD213PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm2, add to ymm3/m256/m32bcst and put result in ymm1.
  EVEX.NDS.256.66.0F38.W0 B8 /r VFMADD231PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, add to ymm1 and put result in ymm1.
  EVEX.NDS.512.66.0F38.W0 98 /r VFMADD132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, add to zmm2 and put result in zmm1.
  EVEX.NDS.512.66.0F38.W0 A8 /r VFMADD213PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm2, add to zmm3/m512/m32bcst and put result in zmm1.
  EVEX.NDS.512.66.0F38.W0 B8 /r VFMADD231PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, add to zmm1 and put result in zmm1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  Performs a set of SIMD multiply-add computation on packed single-precision floating-point values using three source operands and writes the multiply-add results in the destination operand. The destination operand is also the first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD register or a memory location.

  VFMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first source operand to the four, eight or sixteen packed single-precision floating-point values in the third source operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision floating-point values in the second source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  VFMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the four, eight or sixteen packed single-precision floating-point values in the first source operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision floating-point values in the third source operand, performs rounding and stores the resulting the four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  VFMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the four, eight or sixteen packed single-precision floating-point values in the third source operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision floating-point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in reg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is conditionally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  
  

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFMADD132PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 4

  ELSEIF (VEX.256) MAXNUM  8

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMADD213PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 4

  ELSEIF (VEX.256) MAXNUM  8

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] + SRC3[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMADD231PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 4

  ELSEIF (VEX.256) MAXNUM  8

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMADDxxxPS m512 _mm512_fmadd_ps( m512 a, m512 b, m512 c); VFMADDxxxPS m512 _mm512_fmadd_round_ps( m512 a, m512 b, m512 c, int r);

  VFMADDxxxPS m512 _mm512_mask_fmadd_ps( m512 a, mmask16 k, m512 b, m512 c); VFMADDxxxPS m512 _mm512_maskz_fmadd_ps( mmask16 k, m512 a, m512 b, m512 c); VFMADDxxxPS m512 _mm512_mask3_fmadd_ps( m512 a, m512 b, m512 c, mmask16 k); VFMADDxxxPS m512 _mm512_mask_fmadd_round_ps( m512 a, mmask16 k, m512 b, m512 c, int r); VFMADDxxxPS m512 _mm512_maskz_fmadd_round_ps( mmask16 k, m512 a, m512 b, m512 c, int r); VFMADDxxxPS m512 _mm512_mask3_fmadd_round_ps( m512 a, m512 b, m512 c, mmask16 k, int r); VFMADDxxxPS m256 _mm256_mask_fmadd_ps( m256 a, mmask8 k, m256 b, m256 c); VFMADDxxxPS m256 _mm256_maskz_fmadd_ps( mmask8 k, m256 a, m256 b, m256 c); VFMADDxxxPS m256 _mm256_mask3_fmadd_ps( m256 a, m256 b, m256 c, mmask8 k); VFMADDxxxPS m128 _mm_mask_fmadd_ps( m128 a, mmask8 k, m128 b, m128 c);

  VFMADDxxxPS m128 _mm_maskz_fmadd_ps( mmask8 k, m128 a, m128 b, m128 c); VFMADDxxxPS m128 _mm_mask3_fmadd_ps( m128 a, m128 b, m128 c, mmask8 k); VFMADDxxxPS m128 _mm_fmadd_ps ( m128 a, m128 b, m128 c);

  VFMADDxxxPS m256 _mm256_fmadd_ps ( m256 a, m256 b, m256 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of Scalar Double- Precision Floating-Point Values

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.LIG.66.0F38.W1 99 /r VFMADD132SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, add to xmm2 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W1 A9 /r VFMADD213SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm1 and xmm2, add to xmm3/m64 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W1 B9 /r VFMADD231SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, add to xmm1 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 99 /r VFMADD132SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, add to xmm2 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 A9 /r VFMADD213SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm1 and xmm2, add to xmm3/m64 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 B9 /r VFMADD231SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, add to xmm1 and put result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  Performs a SIMD multiply-add computation on the low double-precision floating-point values using three source operands and writes the multiply-add result in the destination operand. The destination operand is also the first source operand. The first and second operand are XMM registers. The third source operand can be an XMM register or a 64-bit memory location.

  VFMADD132SD: Multiplies the low double-precision floating-point value from the first source operand to the low double-precision floating-point value in the third source operand, adds the infinite precision intermediate result to the low double-precision floating-point values in the second source operand, performs rounding and stores the resulting double-precision floating-point value to the destination operand (first source operand).

  VFMADD213SD: Multiplies the low double-precision floating-point value from the second source operand to the low double-precision floating-point value in the first source operand, adds the infinite precision intermediate result to the low double-precision floating-point value in the third source operand, performs rounding and stores the resulting double-precision floating-point value to the destination operand (first source operand).

  VFMADD231SD: Multiplies the low double-precision floating-point value from the second source to the low double- precision floating-point value in the third source operand, adds the infinite precision intermediate result to the low double-precision floating-point value in the first source operand, performs rounding and stores the resulting double-precision floating-point value to the destination operand (first source operand).

  VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

  EVEX encoded version: The low quadword element of the destination is updated according to the writemask.

  
  

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(DEST[63:0]*SRC3[63:0] + SRC2[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  VFMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(SRC2[63:0]*DEST[63:0] + SRC3[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  
  

  VFMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(SRC2[63:0]*SRC3[63:0] + DEST[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  VFMADD132SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0]  MAXVL-1:128RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0]) DEST[127:63]  DEST[127:63]

  DEST[MAXVL-1:128]  0

  
  

  VFMADD213SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0]  RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0]) DEST[127:63]  DEST[127:63]

  DEST[MAXVL-1:128]  0

  
  

  VFMADD231SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0]  RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0]) DEST[127:63]  DEST[127:63]

  DEST[MAXVL-1:128]  0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMADDxxxSD m128d _mm_fmadd_round_sd( m128d a, m128d b, m128d c, int r); VFMADDxxxSD m128d _mm_mask_fmadd_sd( m128d a, mmask8 k, m128d b, m128d c); VFMADDxxxSD m128d _mm_maskz_fmadd_sd( mmask8 k, m128d a, m128d b, m128d c); VFMADDxxxSD m128d _mm_mask3_fmadd_sd( m128d a, m128d b, m128d c, mmask8 k);

  VFMADDxxxSD m128d _mm_mask_fmadd_round_sd( m128d a, mmask8 k, m128d b, m128d c, int r); VFMADDxxxSD m128d _mm_maskz_fmadd_round_sd( mmask8 k, m128d a, m128d b, m128d c, int r); VFMADDxxxSD m128d _mm_mask3_fmadd_round_sd( m128d a, m128d b, m128d c, mmask8 k, int r); VFMADDxxxSD m128d _mm_fmadd_sd ( m128d a, m128d b, m128d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 3. EVEX-encoded instructions, see Exceptions Type E3.

  
  

  VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.LIG.66.0F38.W0 99 /r VFMADD132SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, add to xmm2 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W0 A9 /r VFMADD213SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm1 and xmm2, add to xmm3/m32 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W0 B9 /r VFMADD231SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, add to xmm1 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 99 /r VFMADD132SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, add to xmm2 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 A9 /r VFMADD213SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm1 and xmm2, add to xmm3/m32 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 B9 /r VFMADD231SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, add to xmm1 and put result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  Performs a SIMD multiply-add computation on single-precision floating-point values using three source operands and writes the multiply-add results in the destination operand. The destination operand is also the first source operand. The first and second operands are XMM registers. The third source operand can be a XMM register or a 32-bit memory location.

  VFMADD132SS: Multiplies the low single-precision floating-point value from the first source operand to the low single-precision floating-point value in the third source operand, adds the infinite precision intermediate result to the low single-precision floating-point value in the second source operand, performs rounding and stores the resulting single-precision floating-point value to the destination operand (first source operand).

  VFMADD213SS: Multiplies the low single-precision floating-point value from the second source operand to the low single-precision floating-point value in the first source operand, adds the infinite precision intermediate result to the low single-precision floating-point value in the third source operand, performs rounding and stores the resulting single-precision floating-point value to the destination operand (first source operand).

  VFMADD231SS: Multiplies the low single-precision floating-point value from the second source operand to the low single-precision floating-point value in the third source operand, adds the infinite precision intermediate result to the low single-precision floating-point value in the first source operand, performs rounding and stores the resulting single-precision floating-point value to the destination operand (first source operand).

  VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

  
  

  
  

  EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(DEST[31:0]*SRC3[31:0] + SRC2[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  VFMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(SRC2[31:0]*DEST[31:0] + SRC3[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  
  

  VFMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(SRC2[31:0]*SRC3[31:0] + DEST[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0]] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  VFMADD132SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] + SRC2[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  VFMADD213SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] + SRC3[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  VFMADD231SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] + DEST[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMADDxxxSS m128 _mm_fmadd_round_ss( m128 a, m128 b, m128 c, int r); VFMADDxxxSS m128 _mm_mask_fmadd_ss( m128 a, mmask8 k, m128 b, m128 c); VFMADDxxxSS m128 _mm_maskz_fmadd_ss( mmask8 k, m128 a, m128 b, m128 c); VFMADDxxxSS m128 _mm_mask3_fmadd_ss( m128 a, m128 b, m128 c, mmask8 k);

  VFMADDxxxSS m128 _mm_mask_fmadd_round_ss( m128 a, mmask8 k, m128 b, m128 c, int r); VFMADDxxxSS m128 _mm_maskz_fmadd_round_ss( mmask8 k, m128 a, m128 b, m128 c, int r); VFMADDxxxSS m128 _mm_mask3_fmadd_round_ss( m128 a, m128 b, m128 c, mmask8 k, int r); VFMADDxxxSS m128 _mm_fmadd_ss ( m128 a, m128 b, m128 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 3. EVEX-encoded instructions, see Exceptions Type E3.

  
  

  VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.128.66.0F38.W1 96 /r VFMADDSUB132PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, add/subtract elements in xmm2 and put result in xmm1.
  VEX.DDS.128.66.0F38.W1 A6 /r VFMADDSUB213PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/mem and put result in xmm1.
  VEX.DDS.128.66.0F38.W1 B6 /r VFMADDSUB231PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, add/subtract elements in xmm1 and put result in xmm1.
  VEX.DDS.256.66.0F38.W1 96 /r VFMADDSUB132PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, add/subtract elements in ymm2 and put result in ymm1.
  VEX.DDS.256.66.0F38.W1 A6 /r VFMADDSUB213PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/mem and put result in ymm1.
  VEX.DDS.256.66.0F38.W1 B6 /r VFMADDSUB231PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, add/subtract elements in ymm1 and put result in ymm1.
  EVEX.DDS.128.66.0F38.W1 A6 /r VFMADDSUB213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1.
  EVEX.DDS.128.66.0F38.W1 B6 /r VFMADDSUB231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, add/subtract elements in xmm1 and put result in xmm1 subject to writemask k1.
  EVEX.DDS.128.66.0F38.W1 96 /r VFMADDSUB132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, add/subtract elements in xmm2 and put result in xmm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W1 A6 /r VFMADDSUB213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W1 B6 /r VFMADDSUB231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, add/subtract elements in ymm1 and put result in ymm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W1 96 /r VFMADDSUB132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, add/subtract elements in ymm2 and put result in ymm1 subject to writemask k1.

  
  

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.DDS.512.66.0F38.W1 A6 /r VFMADDSUB213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1and zmm2, add/subtract elements in zmm3/m512/m64bcst and put result in zmm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W1 B6 /r VFMADDSUB231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, add/subtract elements in zmm1 and put result in zmm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W1 96 /r VFMADDSUB132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, add/subtract elements in zmm2 and put result in zmm1 subject to writemask k1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFMADDSUB132PD: Multiplies the two, four, or eight packed double-precision floating-point values from the first source operand to the two or four packed double-precision floating-point values in the third source operand. From the infinite precision intermediate result, adds the odd double-precision floating-point elements and subtracts the even double-precision floating-point values in the second source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).

  VFMADDSUB213PD: Multiplies the two, four, or eight packed double-precision floating-point values from the second source operand to the two or four packed double-precision floating-point values in the first source operand. From the infinite precision intermediate result, adds the odd double-precision floating-point elements and subtracts the even double-precision floating-point values in the third source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).

  VFMADDSUB231PD: Multiplies the two, four, or eight packed double-precision floating-point values from the second source operand to the two or four packed double-precision floating-point values in the third source operand. From the infinite precision intermediate result, adds the odd double-precision floating-point elements and subtracts the even double-precision floating-point values in the first source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  
  

  
  

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFMADDSUB132PD DEST, SRC2, SRC3

  IF (VEX.128) THEN

  DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0]) DEST[127:64] RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64]) DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256)

  DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0]) DEST[127:64] RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])

  DEST[191:128] RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] - SRC2[191:128]) DEST[255:192] RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] + SRC2[255:192]

  FI

  
  

  VFMADDSUB213PD DEST, SRC2, SRC3

  IF (VEX.128) THEN

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0]) DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64]) DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256)

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0]) DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])

  DEST[191:128] RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] - SRC3[191:128]) DEST[255:192] RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] + SRC3[255:192]

  FI

  
  

  VFMADDSUB231PD DEST, SRC2, SRC3

  IF (VEX.128) THEN

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0]) DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64]) DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256)

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0]) DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])

  DEST[191:128] RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] - DEST[191:128]) DEST[255:192] RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] + DEST[255:192]

  FI

  
  

  
  

  VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+63:i] 

  RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i]) ELSE DEST[i+63:i] 

  RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])

  FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])

  FI;

  FI

  
  

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i]) ELSE DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i]) FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i]) FI;

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i]) ELSE DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])

  FI; ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])

  FI;

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMADDSUBxxxPD m512d _mm512_fmaddsub_pd( m512d a, m512d b, m512d c); VFMADDSUBxxxPD m512d _mm512_fmaddsub_round_pd( m512d a, m512d b, m512d c, int r); VFMADDSUBxxxPD m512d _mm512_mask_fmaddsub_pd( m512d a, mmask8 k, m512d b, m512d c);

  VFMADDSUBxxxPD m512d _mm512_maskz_fmaddsub_pd( mmask8 k, m512d a, m512d b, m512d c); VFMADDSUBxxxPD m512d _mm512_mask3_fmaddsub_pd( m512d a, m512d b, m512d c, mmask8 k); VFMADDSUBxxxPD m512d _mm512_mask_fmaddsub_round_pd( m512d a, mmask8 k, m512d b, m512d c, int r); VFMADDSUBxxxPD m512d _mm512_maskz_fmaddsub_round_pd( mmask8 k, m512d a, m512d b, m512d c, int r); VFMADDSUBxxxPD m512d _mm512_mask3_fmaddsub_round_pd( m512d a, m512d b, m512d c, mmask8 k, int r); VFMADDSUBxxxPD m256d _mm256_mask_fmaddsub_pd( m256d a, mmask8 k, m256d b, m256d c); VFMADDSUBxxxPD m256d _mm256_maskz_fmaddsub_pd( mmask8 k, m256d a, m256d b, m256d c); VFMADDSUBxxxPD m256d _mm256_mask3_fmaddsub_pd( m256d a, m256d b, m256d c, mmask8 k); VFMADDSUBxxxPD m128d _mm_mask_fmaddsub_pd( m128d a, mmask8 k, m128d b, m128d c); VFMADDSUBxxxPD m128d _mm_maskz_fmaddsub_pd( mmask8 k, m128d a, m128d b, m128d c); VFMADDSUBxxxPD m128d _mm_mask3_fmaddsub_pd( m128d a, m128d b, m128d c, mmask8 k); VFMADDSUBxxxPD m128d _mm_fmaddsub_pd ( m128d a, m128d b, m128d c);

  VFMADDSUBxxxPD m256d _mm256_fmaddsub_pd ( m256d a, m256d b, m256d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.128.66.0F38.W0 96 /r VFMADDSUB132PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, add/subtract elements in xmm2 and put result in xmm1.
  VEX.DDS.128.66.0F38.W0 A6 /r VFMADDSUB213PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/mem and put result in xmm1.
  VEX.DDS.128.66.0F38.W0 B6 /r VFMADDSUB231PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, add/subtract elements in xmm1 and put result in xmm1.
  VEX.DDS.256.66.0F38.W0 96 /r VFMADDSUB132PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, add/subtract elements in ymm2 and put result in ymm1.
  VEX.DDS.256.66.0F38.W0 A6 /r VFMADDSUB213PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/mem and put result in ymm1.
  VEX.DDS.256.66.0F38.W0 B6 /r VFMADDSUB231PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, add/subtract elements in ymm1 and put result in ymm1.
  EVEX.DDS.128.66.0F38.W0 A6 /r VFMADDSUB213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/m128/m32bcst and put result in xmm1 subject to writemask k1.
  EVEX.DDS.128.66.0F38.W0 B6 /r VFMADDSUB231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, add/subtract elements in xmm1 and put result in xmm1 subject to writemask k1.
  EVEX.DDS.128.66.0F38.W0 96 /r VFMADDSUB132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, add/subtract elements in zmm2 and put result in xmm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W0 A6 /r VFMADDSUB213PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/m256/m32bcst and put result in ymm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W0 B6 /r VFMADDSUB231PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, add/subtract elements in ymm1 and put result in ymm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W0 96 /r VFMADDSUB132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, add/subtract elements in ymm2 and put result in ymm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W0 A6 /r VFMADDSUB213PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm2, add/subtract elements in zmm3/m512/m32bcst and put result in zmm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W0 B6 /r VFMADDSUB231PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, add/subtract elements in zmm1 and put result in zmm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W0 96 /r VFMADDSUB132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, add/subtract elements in zmm2 and put result in zmm1 subject to writemask k1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFMADDSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first source operand to the corresponding packed single-precision floating-point values in the third source operand.

  From the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts the even single-precision floating-point values in the second source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).

  VFMADDSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the corresponding packed single-precision floating-point values in the first source operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts the even single-precision floating-point values in the third source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).

  VFMADDSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the corresponding packed single-precision floating-point values in the third source operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts the even single-precision floating-point values in the first source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFMADDSUB132PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM -1{

  n  64*i;

  DEST[n+31:n] RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n]) DEST[n+63:n+32] RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] + SRC2[n+63:n+32])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMADDSUB213PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM -1{

  n  64*i;

  DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n]) DEST[n+63:n+32] RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] + SRC3[n+63:n+32])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFMADDSUB231PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM -1{

  n  64*i;

  DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n]) DEST[n+63:n+32] RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] + DEST[n+63:n+32])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) (4, 128), (8, 256),= (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+31:i] 

  RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i]) ELSE DEST[i+31:i] 

  RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i]) FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i]) FI;

  FI

  
  

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i]) ELSE DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i]) FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i]) FI;

  
  

  
  

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i]) ELSE DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i]) FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i]) FI;

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMADDSUBxxxPS m512 _mm512_fmaddsub_ps( m512 a, m512 b, m512 c); VFMADDSUBxxxPS m512 _mm512_fmaddsub_round_ps( m512 a, m512 b, m512 c, int r);

  VFMADDSUBxxxPS m512 _mm512_mask_fmaddsub_ps( m512 a, mmask16 k, m512 b, m512 c); VFMADDSUBxxxPS m512 _mm512_maskz_fmaddsub_ps( mmask16 k, m512 a, m512 b, m512 c); VFMADDSUBxxxPS m512 _mm512_mask3_fmaddsub_ps( m512 a, m512 b, m512 c, mmask16 k); VFMADDSUBxxxPS m512 _mm512_mask_fmaddsub_round_ps( m512 a, mmask16 k, m512 b, m512 c, int r); VFMADDSUBxxxPS m512 _mm512_maskz_fmaddsub_round_ps( mmask16 k, m512 a, m512 b, m512 c, int r); VFMADDSUBxxxPS m512 _mm512_mask3_fmaddsub_round_ps( m512 a, m512 b, m512 c, mmask16 k, int r); VFMADDSUBxxxPS m256 _mm256_mask_fmaddsub_ps( m256 a, mmask8 k, m256 b, m256 c); VFMADDSUBxxxPS m256 _mm256_maskz_fmaddsub_ps( mmask8 k, m256 a, m256 b, m256 c); VFMADDSUBxxxPS m256 _mm256_mask3_fmaddsub_ps( m256 a, m256 b, m256 c, mmask8 k); VFMADDSUBxxxPS m128 _mm_mask_fmaddsub_ps( m128 a, mmask8 k, m128 b, m128 c); VFMADDSUBxxxPS m128 _mm_maskz_fmaddsub_ps( mmask8 k, m128 a, m128 b, m128 c); VFMADDSUBxxxPS m128 _mm_mask3_fmaddsub_ps( m128 a, m128 b, m128 c, mmask8 k); VFMADDSUBxxxPS m128 _mm_fmaddsub_ps ( m128 a, m128 b, m128 c);

  VFMADDSUBxxxPS m256 _mm256_fmaddsub_ps ( m256 a, m256 b, m256 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.128.66.0F38.W1 97 /r VFMSUBADD132PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, subtract/add elements in xmm2 and put result in xmm1.
  VEX.DDS.128.66.0F38.W1 A7 /r VFMSUBADD213PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm2, subtract/add elements in xmm3/mem and put result in xmm1.
  VEX.DDS.128.66.0F38.W1 B7 /r VFMSUBADD231PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, subtract/add elements in xmm1 and put result in xmm1.
  VEX.DDS.256.66.0F38.W1 97 /r VFMSUBADD132PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, subtract/add elements in ymm2 and put result in ymm1.
  VEX.DDS.256.66.0F38.W1 A7 /r VFMSUBADD213PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm2, subtract/add elements in ymm3/mem and put result in ymm1.
  VEX.DDS.256.66.0F38.W1 B7 /r VFMSUBADD231PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, subtract/add elements in ymm1 and put result in ymm1.
  EVEX.DDS.128.66.0F38.W1 97 /r VFMSUBADD132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, subtract/add elements in xmm2 and put result in xmm1 subject to writemask k1.
  EVEX.DDS.128.66.0F38.W1 A7 /r VFMSUBADD213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm2, subtract/add elements in xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1.
  EVEX.DDS.128.66.0F38.W1 B7 /r VFMSUBADD231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, subtract/add elements in xmm1 and put result in xmm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W1 97 /r VFMSUBADD132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, subtract/add elements in ymm2 and put result in ymm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W1 A7 /r VFMSUBADD213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm2, subtract/add elements in ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W1 B7 /r VFMSUBADD231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, subtract/add elements in ymm1 and put result in ymm1 subject to writemask k1.

  
  

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.DDS.512.66.0F38.W1 97 /r VFMSUBADD132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, subtract/add elements in zmm2 and put result in zmm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W1 A7 /r VFMSUBADD213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm2, subtract/add elements in zmm3/m512/m64bcst and put result in zmm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W1 B7 /r VFMSUBADD231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, subtract/add elements in zmm1 and put result in zmm1 subject to writemask k1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFMSUBADD132PD: Multiplies the two, four, or eight packed double-precision floating-point values from the first source operand to the two or four packed double-precision floating-point values in the third source operand. From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the even double-precision floating-point values in the second source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).

  VFMSUBADD213PD: Multiplies the two, four, or eight packed double-precision floating-point values from the second source operand to the two or four packed double-precision floating-point values in the first source operand. From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the even double-precision floating-point values in the third source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).

  VFMSUBADD231PD: Multiplies the two, four, or eight packed double-precision floating-point values from the second source operand to the two or four packed double-precision floating-point values in the third source operand. From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the even double-precision floating-point values in the first source operand, performs rounding and stores the resulting two or four packed double-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition- ally updated with write mask k1.

  
  

  
  

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFMSUBADD132PD DEST, SRC2, SRC3

  IF (VEX.128) THEN

  DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0]) DEST[127:64] RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64]) DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256)

  DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0]) DEST[127:64] RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])

  DEST[191:128] RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] + SRC2[191:128]) DEST[255:192] RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] - SRC2[255:192]

  FI

  
  

  VFMSUBADD213PD DEST, SRC2, SRC3 IF (VEX.128) THEN

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0]) DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64]) DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256)

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0]) DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])

  DEST[191:128] RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] + SRC3[191:128]) DEST[255:192] RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] - SRC3[255:192]

  FI

  
  

  VFMSUBADD231PD DEST, SRC2, SRC3

  IF (VEX.128) THEN

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0]) DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64]) DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256)

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0]) DEST[127:64] RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])

  DEST[191:128] RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] + DEST[191:128]) DEST[255:192] RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] - DEST[255:192]

  FI

  
  

  
  

  VFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+63:i] 

  RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i]) ELSE DEST[i+63:i] 

  RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i]) FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i]) FI;

  FI

  
  

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i]) ELSE DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i]) FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i]) FI;

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i]) ELSE DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i]) FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])

  
  

  
  

  FI ELSE

  ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i]) FI;

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMSUBADDxxxPD m512d _mm512_fmsubadd_pd( m512d a, m512d b, m512d c); VFMSUBADDxxxPD m512d _mm512_fmsubadd_round_pd( m512d a, m512d b, m512d c, int r); VFMSUBADDxxxPD m512d _mm512_mask_fmsubadd_pd( m512d a, mmask8 k, m512d b, m512d c);

  VFMSUBADDxxxPD m512d _mm512_maskz_fmsubadd_pd( mmask8 k, m512d a, m512d b, m512d c); VFMSUBADDxxxPD m512d _mm512_mask3_fmsubadd_pd( m512d a, m512d b, m512d c, mmask8 k); VFMSUBADDxxxPD m512d _mm512_mask_fmsubadd_round_pd( m512d a, mmask8 k, m512d b, m512d c, int r); VFMSUBADDxxxPD m512d _mm512_maskz_fmsubadd_round_pd( mmask8 k, m512d a, m512d b, m512d c, int r); VFMSUBADDxxxPD m512d _mm512_mask3_fmsubadd_round_pd( m512d a, m512d b, m512d c, mmask8 k, int r); VFMSUBADDxxxPD m256d _mm256_mask_fmsubadd_pd( m256d a, mmask8 k, m256d b, m256d c); VFMSUBADDxxxPD m256d _mm256_maskz_fmsubadd_pd( mmask8 k, m256d a, m256d b, m256d c); VFMSUBADDxxxPD m256d _mm256_mask3_fmsubadd_pd( m256d a, m256d b, m256d c, mmask8 k); VFMSUBADDxxxPD m128d _mm_mask_fmsubadd_pd( m128d a, mmask8 k, m128d b, m128d c); VFMSUBADDxxxPD m128d _mm_maskz_fmsubadd_pd( mmask8 k, m128d a, m128d b, m128d c); VFMSUBADDxxxPD m128d _mm_mask3_fmsubadd_pd( m128d a, m128d b, m128d c, mmask8 k); VFMSUBADDxxxPD m128d _mm_fmsubadd_pd ( m128d a, m128d b, m128d c);

  VFMSUBADDxxxPD m256d _mm256_fmsubadd_pd ( m256d a, m256d b, m256d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2.

  EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.128.66.0F38.W0 97 /r VFMSUBADD132PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, subtract/add elements in xmm2 and put result in xmm1.
  VEX.DDS.128.66.0F38.W0 A7 /r VFMSUBADD213PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm2, subtract/add elements in xmm3/mem and put result in xmm1.
  VEX.DDS.128.66.0F38.W0 B7 /r VFMSUBADD231PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, subtract/add elements in xmm1 and put result in xmm1.
  VEX.DDS.256.66.0F38.W0 97 /r VFMSUBADD132PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, subtract/add elements in ymm2 and put result in ymm1.
  VEX.DDS.256.66.0F38.W0 A7 /r VFMSUBADD213PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm2, subtract/add elements in ymm3/mem and put result in ymm1.
  VEX.DDS.256.66.0F38.W0 B7 /r VFMSUBADD231PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, subtract/add elements in ymm1 and put result in ymm1.
  EVEX.DDS.128.66.0F38.W0 97 /r VFMSUBADD132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, subtract/add elements in xmm2 and put result in xmm1 subject to writemask k1.
  EVEX.DDS.128.66.0F38.W0 A7 /r VFMSUBADD213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm2, subtract/add elements in xmm3/m128/m32bcst and put result in xmm1 subject to writemask k1.
  EVEX.DDS.128.66.0F38.W0 B7 /r VFMSUBADD231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, subtract/add elements in xmm1 and put result in xmm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W0 97 /r VFMSUBADD132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, subtract/add elements in ymm2 and put result in ymm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W0 A7 /r VFMSUBADD213PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm2, subtract/add elements in ymm3/m256/m32bcst and put result in ymm1 subject to writemask k1.
  EVEX.DDS.256.66.0F38.W0 B7 /r VFMSUBADD231PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, subtract/add elements in ymm1 and put result in ymm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W0 97 /r VFMSUBADD132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, subtract/add elements in zmm2 and put result in zmm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W0 A7 /r VFMSUBADD213PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm2, subtract/add elements in zmm3/m512/m32bcst and put result in zmm1 subject to writemask k1.
  EVEX.DDS.512.66.0F38.W0 B7 /r VFMSUBADD231PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, subtract/add elements in zmm1 and put result in zmm1 subject to writemask k1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFMSUBADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first source operand to the corresponding packed single-precision floating-point values in the third source operand.

  From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements and adds the even single-precision floating-point values in the second source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).

  VFMSUBADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the corresponding packed single-precision floating-point values in the first source operand. From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements and adds the even single-precision floating-point values in the third source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).

  VFMSUBADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the corresponding packed single-precision floating-point values in the third source operand. From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements and adds the even single-precision floating-point values in the first source operand, performs rounding and stores the resulting packed single-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFMSUBADD132PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM -1{

  n  64*i;

  DEST[n+31:n] RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n]) DEST[n+63:n+32] RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] -SRC2[n+63:n+32])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMSUBADD213PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM -1{

  n  64*i;

  DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] +SRC3[n+31:n]) DEST[n+63:n+32] RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] -SRC3[n+63:n+32])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMSUBADD231PS DEST, SRC2, SRC3

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM -1{

  n  64*i;

  DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n]) DEST[n+63:n+32] RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] -DEST[n+63:n+32])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128] 0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+31:i] 

  RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i]) ELSE DEST[i+31:i] 

  RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i]  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i]) ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])

  FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i]) FI;

  FI

  
  

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i]) ELSE DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0]) ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])

  
  

  FI ELSE

  FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0]) FI;

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even*

  THEN DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i]) ELSE DEST[i+31:i] 

  RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])

  FI ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF j *is even* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i]) ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])

  
  

  FI ELSE

  FI;

  ELSE

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i]) FI;

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMSUBADDxxxPS m512 _mm512_fmsubadd_ps( m512 a, m512 b, m512 c); VFMSUBADDxxxPS m512 _mm512_fmsubadd_round_ps( m512 a, m512 b, m512 c, int r);

  VFMSUBADDxxxPS m512 _mm512_mask_fmsubadd_ps( m512 a, mmask16 k, m512 b, m512 c); VFMSUBADDxxxPS m512 _mm512_maskz_fmsubadd_ps( mmask16 k, m512 a, m512 b, m512 c); VFMSUBADDxxxPS m512 _mm512_mask3_fmsubadd_ps( m512 a, m512 b, m512 c, mmask16 k); VFMSUBADDxxxPS m512 _mm512_mask_fmsubadd_round_ps( m512 a, mmask16 k, m512 b, m512 c, int r); VFMSUBADDxxxPS m512 _mm512_maskz_fmsubadd_round_ps( mmask16 k, m512 a, m512 b, m512 c, int r); VFMSUBADDxxxPS m512 _mm512_mask3_fmsubadd_round_ps( m512 a, m512 b, m512 c, mmask16 k, int r); VFMSUBADDxxxPS m256 _mm256_mask_fmsubadd_ps( m256 a, mmask8 k, m256 b, m256 c); VFMSUBADDxxxPS m256 _mm256_maskz_fmsubadd_ps( mmask8 k, m256 a, m256 b, m256 c); VFMSUBADDxxxPS m256 _mm256_mask3_fmsubadd_ps( m256 a, m256 b, m256 c, mmask8 k); VFMSUBADDxxxPS m128 _mm_mask_fmsubadd_ps( m128 a, mmask8 k, m128 b, m128 c); VFMSUBADDxxxPS m128 _mm_maskz_fmsubadd_ps( mmask8 k, m128 a, m128 b, m128 c); VFMSUBADDxxxPS m128 _mm_mask3_fmsubadd_ps( m128 a, m128 b, m128 c, mmask8 k); VFMSUBADDxxxPS m128 _mm_fmsubadd_ps ( m128 a, m128 b, m128 c);

  VFMSUBADDxxxPS m256 _mm256_fmsubadd_ps ( m256 a, m256 b, m256 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double- Precision Floating-Point Values

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.NDS.128.66.0F38.W1 9A /r VFMSUB132PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, subtract xmm2 and put result in xmm1.
  VEX.NDS.128.66.0F38.W1 AA /r VFMSUB213PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm2, subtract xmm3/mem and put result in xmm1.
  VEX.NDS.128.66.0F38.W1 BA /r VFMSUB231PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, subtract xmm1 and put result in xmm1.
  VEX.NDS.256.66.0F38.W1 9A /r VFMSUB132PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, subtract ymm2 and put result in ymm1.
  VEX.NDS.256.66.0F38.W1 AA /r VFMSUB213PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm2, subtract ymm3/mem and put result in ymm1.
  VEX.NDS.256.66.0F38.W1 BA /r VFMSUB231PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, subtract ymm1 and put result in ymm1.S
  EVEX.NDS.128.66.0F38.W1 9A /r VFMSUB132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, subtract xmm2 and put result in xmm1 subject to writemask k1.
  EVEX.NDS.128.66.0F38.W1 AA /r VFMSUB213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm2, subtract xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1.
  EVEX.NDS.128.66.0F38.W1 BA /r VFMSUB231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, subtract xmm1 and put result in xmm1 subject to writemask k1.
  EVEX.NDS.256.66.0F38.W1 9A /r VFMSUB132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, subtract ymm2 and put result in ymm1 subject to writemask k1.
  EVEX.NDS.256.66.0F38.W1 AA /r VFMSUB213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm2, subtract ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1.
  EVEX.NDS.256.66.0F38.W1 BA /r VFMSUB231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, subtract ymm1 and put result in ymm1 subject to writemask k1.
  EVEX.NDS.512.66.0F38.W1 9A /r VFMSUB132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, subtract zmm2 and put result in zmm1 subject to writemask k1.
  EVEX.NDS.512.66.0F38.W1 AA /r VFMSUB213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm2, subtract zmm3/m512/m64bcst and put result in zmm1 subject to writemask k1.
  EVEX.NDS.512.66.0F38.W1 BA /r VFMSUB231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, subtract zmm1 and put result in zmm1 subject to writemask k1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  Performs a set of SIMD multiply-subtract computation on packed double-precision floating-point values using three source operands and writes the multiply-subtract results in the destination operand. The destination operand is also the first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD register or a memory location.

  VFMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source operand to the two, four or eight packed double-precision floating-point values in the third source operand. From the infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-point values in the second source operand, performs rounding and stores the resulting two, four or eight packed double- precision floating-point values to the destination operand (first source operand).

  VFMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source operand to the two, four or eight packed double-precision floating-point values in the first source operand. From the infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating- point values in the third source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  VFMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source to the two, four or eight packed double-precision floating-point values in the third source operand. From the infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-point values in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  
  

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFMSUB132PD DEST, SRC2, SRC3 (VEX encoded versions)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] - SRC2[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMSUB213PD DEST, SRC2, SRC3 (VEX encoded versions)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] - SRC3[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMSUB231PD DEST, SRC2, SRC3 (VEX encoded versions)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] - DEST[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])

  +31:i])

  
  

  ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i]) ELSE

  DEST[i+63:i]  RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMSUBxxxPD m512d _mm512_fmsub_pd( m512d a, m512d b, m512d c); VFMSUBxxxPD m512d _mm512_fmsub_round_pd( m512d a, m512d b, m512d c, int r);

  VFMSUBxxxPD m512d _mm512_mask_fmsub_pd( m512d a, mmask8 k, m512d b, m512d c); VFMSUBxxxPD m512d _mm512_maskz_fmsub_pd( mmask8 k, m512d a, m512d b, m512d c); VFMSUBxxxPD m512d _mm512_mask3_fmsub_pd( m512d a, m512d b, m512d c, mmask8 k); VFMSUBxxxPD m512d _mm512_mask_fmsub_round_pd( m512d a, mmask8 k, m512d b, m512d c, int r); VFMSUBxxxPD m512d _mm512_maskz_fmsub_round_pd( mmask8 k, m512d a, m512d b, m512d c, int r); VFMSUBxxxPD m512d _mm512_mask3_fmsub_round_pd( m512d a, m512d b, m512d c, mmask8 k, int r); VFMSUBxxxPD m256d _mm256_mask_fmsub_pd( m256d a, mmask8 k, m256d b, m256d c); VFMSUBxxxPD m256d _mm256_maskz_fmsub_pd( mmask8 k, m256d a, m256d b, m256d c); VFMSUBxxxPD m256d _mm256_mask3_fmsub_pd( m256d a, m256d b, m256d c, mmask8 k); VFMSUBxxxPD m128d _mm_mask_fmsub_pd( m128d a, mmask8 k, m128d b, m128d c);

  VFMSUBxxxPD m128d _mm_maskz_fmsub_pd( mmask8 k, m128d a, m128d b, m128d c); VFMSUBxxxPD m128d _mm_mask3_fmsub_pd( m128d a, m128d b, m128d c, mmask8 k); VFMSUBxxxPD m128d _mm_fmsub_pd ( m128d a, m128d b, m128d c);

  VFMSUBxxxPD m256d _mm256_fmsub_pd ( m256d a, m256d b, m256d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single- Precision Floating-Point Values

  Opcode/ Instruction	Op/E n	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.NDS.128.66.0F38.W0 9A /r VFMSUB132PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, subtract xmm2 and put result in xmm1.
  VEX.NDS.128.66.0F38.W0 AA /r VFMSUB213PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm2, subtract xmm3/mem and put result in xmm1.
  VEX.NDS.128.66.0F38.W0 BA /r VFMSUB231PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, subtract xmm1 and put result in xmm1.
  VEX.NDS.256.66.0F38.W0 9A /r VFMSUB132PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, subtract ymm2 and put result in ymm1.
  VEX.NDS.256.66.0F38.W0 AA /r VFMSUB213PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm2, subtract ymm3/mem and put result in ymm1.
  VEX.NDS.256.66.0F38.0 BA /r VFMSUB231PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, subtract ymm1 and put result in ymm1.
  EVEX.NDS.128.66.0F38.W0 9A /r VFMSUB132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, subtract xmm2 and put result in xmm1.
  EVEX.NDS.128.66.0F38.W0 AA /r VFMSUB213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm2, subtract xmm3/m128/m32bcst and put result in xmm1.
  EVEX.NDS.128.66.0F38.W0 BA /r VFMSUB231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, subtract xmm1 and put result in xmm1.
  EVEX.NDS.256.66.0F38.W0 9A /r VFMSUB132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, subtract ymm2 and put result in ymm1.
  EVEX.NDS.256.66.0F38.W0 AA /r VFMSUB213PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm2, subtract ymm3/m256/m32bcst and put result in ymm1.
  EVEX.NDS.256.66.0F38.W0 BA /r VFMSUB231PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, subtract ymm1 and put result in ymm1.
  EVEX.NDS.512.66.0F38.W0 9A /r VFMSUB132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, subtract zmm2 and put result in zmm1.
  EVEX.NDS.512.66.0F38.W0 AA /r VFMSUB213PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm2, subtract zmm3/m512/m32bcst and put result in zmm1.
  EVEX.NDS.512.66.0F38.W0 BA /r VFMSUB231PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, subtract zmm1 and put result in zmm1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  Performs a set of SIMD multiply-subtract computation on packed single-precision floating-point values using three source operands and writes the multiply-subtract results in the destination operand. The destination operand is also the first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD register or a memory location.

  VFMSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first source operand to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision floating-point values in the second source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  VFMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the four, eight or sixteen packed single-precision floating-point values in the first source operand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision floating-point values in the third source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  VFMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision floating-point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed single- precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  
  

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i]) ELSE

  DEST[i+31:i]  RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMSUBxxxPS m512 _mm512_fmsub_ps( m512 a, m512 b, m512 c); VFMSUBxxxPS m512 _mm512_fmsub_round_ps( m512 a, m512 b, m512 c, int r);

  VFMSUBxxxPS m512 _mm512_mask_fmsub_ps( m512 a, mmask16 k, m512 b, m512 c); VFMSUBxxxPS m512 _mm512_maskz_fmsub_ps( mmask16 k, m512 a, m512 b, m512 c); VFMSUBxxxPS m512 _mm512_mask3_fmsub_ps( m512 a, m512 b, m512 c, mmask16 k); VFMSUBxxxPS m512 _mm512_mask_fmsub_round_ps( m512 a, mmask16 k, m512 b, m512 c, int r); VFMSUBxxxPS m512 _mm512_maskz_fmsub_round_ps( mmask16 k, m512 a, m512 b, m512 c, int r); VFMSUBxxxPS m512 _mm512_mask3_fmsub_round_ps( m512 a, m512 b, m512 c, mmask16 k, int r); VFMSUBxxxPS m256 _mm256_mask_fmsub_ps( m256 a, mmask8 k, m256 b, m256 c); VFMSUBxxxPS m256 _mm256_maskz_fmsub_ps( mmask8 k, m256 a, m256 b, m256 c); VFMSUBxxxPS m256 _mm256_mask3_fmsub_ps( m256 a, m256 b, m256 c, mmask8 k); VFMSUBxxxPS m128 _mm_mask_fmsub_ps( m128 a, mmask8 k, m128 b, m128 c);

  VFMSUBxxxPS m128 _mm_maskz_fmsub_ps( mmask8 k, m128 a, m128 b, m128 c); VFMSUBxxxPS m128 _mm_mask3_fmsub_ps( m128 a, m128 b, m128 c, mmask8 k); VFMSUBxxxPS m128 _mm_fmsub_ps ( m128 a, m128 b, m128 c);

  VFMSUBxxxPS m256 _mm256_fmsub_ps ( m256 a, m256 b, m256 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double- Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.LIG.66.0F38.W1 9B /r VFMSUB132SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, subtract xmm2 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W1 AB /r VFMSUB213SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm1 and xmm2, subtract xmm3/m64 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W1 BB /r VFMSUB231SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, subtract xmm1 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 9B /r VFMSUB132SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, subtract xmm2 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 AB /r VFMSUB213SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm1 and xmm2, subtract xmm3/m64 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 BB /r VFMSUB231SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, subtract xmm1 and put result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  Performs a SIMD multiply-subtract computation on the low packed double-precision floating-point values using three source operands and writes the multiply-subtract result in the destination operand. The destination operand is also the first source operand. The second operand must be a XMM register. The third source operand can be a XMM register or a 64-bit memory location.

  VFMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to the low packed double-precision floating-point value in the third source operand. From the infinite precision interme- diate result, subtracts the low packed double-precision floating-point values in the second source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VFMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand to the low packed double-precision floating-point value in the first source operand. From the infinite precision inter- mediate result, subtracts the low packed double-precision floating-point value in the third source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VFMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low packed double-precision floating-point value in the third source operand. From the infinite precision intermediate result, subtracts the low packed double-precision floating-point value in the first source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

  
  

  
  

  EVEX encoded version: The low quadword element of the destination is updated according to the writemask.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFMSUB132SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(DEST[63:0]*SRC3[63:0] - SRC2[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  VFMSUB213SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(SRC2[63:0]*DEST[63:0] - SRC3[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  
  

  VFMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(SRC2[63:0]*SRC3[63:0] - DEST[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  VFMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  VFMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  VFMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMSUBxxxSD m128d _mm_fmsub_round_sd( m128d a, m128d b, m128d c, int r); VFMSUBxxxSD m128d _mm_mask_fmsub_sd( m128d a, mmask8 k, m128d b, m128d c); VFMSUBxxxSD m128d _mm_maskz_fmsub_sd( mmask8 k, m128d a, m128d b, m128d c); VFMSUBxxxSD m128d _mm_mask3_fmsub_sd( m128d a, m128d b, m128d c, mmask8 k);

  VFMSUBxxxSD m128d _mm_mask_fmsub_round_sd( m128d a, mmask8 k, m128d b, m128d c, int r); VFMSUBxxxSD m128d _mm_maskz_fmsub_round_sd( mmask8 k, m128d a, m128d b, m128d c, int r); VFMSUBxxxSD m128d _mm_mask3_fmsub_round_sd( m128d a, m128d b, m128d c, mmask8 k, int r); VFMSUBxxxSD m128d _mm_fmsub_sd ( m128d a, m128d b, m128d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 3. EVEX-encoded instructions, see Exceptions Type E3.

  
  

  VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single- Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.LIG.66.0F38.W0 9B /r VFMSUB132SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, subtract xmm2 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W0 AB /r VFMSUB213SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm1 and xmm2, subtract xmm3/m32 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W0 BB /r VFMSUB231SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, subtract xmm1 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 9B /r VFMSUB132SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, subtract xmm2 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 AB /r VFMSUB213SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm1 and xmm2, subtract xmm3/m32 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 BB /r VFMSUB231SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, subtract xmm1 and put result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  Performs a SIMD multiply-subtract computation on the low packed single-precision floating-point values using three source operands and writes the multiply-subtract result in the destination operand. The destination operand is also the first source operand. The second operand must be a XMM register. The third source operand can be a XMM register or a 32-bit memory location.

  VFMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to the low packed single-precision floating-point value in the third source operand. From the infinite precision interme- diate result, subtracts the low packed single-precision floating-point values in the second source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VFMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to the low packed single-precision floating-point value in the first source operand. From the infinite precision interme- diate result, subtracts the low packed single-precision floating-point value in the third source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VFMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low packed single-precision floating-point value in the third source operand. From the infinite precision intermediate result, subtracts the low packed single-precision floating-point value in the first source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

  
  

  
  

  EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(DEST[31:0]*SRC3[31:0] - SRC2[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  VFMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(SRC2[31:0]*DEST[31:0] - SRC3[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  
  

  VFMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(SRC2[31:0]*SRC3[63:0] - DEST[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  VFMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] - SRC2[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  VFMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] - SRC3[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  VFMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] - DEST[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFMSUBxxxSS m128 _mm_fmsub_round_ss( m128 a, m128 b, m128 c, int r); VFMSUBxxxSS m128 _mm_mask_fmsub_ss( m128 a, mmask8 k, m128 b, m128 c); VFMSUBxxxSS m128 _mm_maskz_fmsub_ss( mmask8 k, m128 a, m128 b, m128 c); VFMSUBxxxSS m128 _mm_mask3_fmsub_ss( m128 a, m128 b, m128 c, mmask8 k);

  VFMSUBxxxSS m128 _mm_mask_fmsub_round_ss( m128 a, mmask8 k, m128 b, m128 c, int r); VFMSUBxxxSS m128 _mm_maskz_fmsub_round_ss( mmask8 k, m128 a, m128 b, m128 c, int r); VFMSUBxxxSS m128 _mm_mask3_fmsub_round_ss( m128 a, m128 b, m128 c, mmask8 k, int r); VFMSUBxxxSS m128 _mm_fmsub_ss ( m128 a, m128 b, m128 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 3. EVEX-encoded instructions, see Exceptions Type E3.

  
  

  VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.NDS.128.66.0F38.W1 9C /r VFNMADD132PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and add to xmm2 and put result in xmm1.
  VEX.NDS.128.66.0F38.W1 AC /r VFNMADD213PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/mem and put result in xmm1.
  VEX.NDS.128.66.0F38.W1 BC /r VFNMADD231PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and add to xmm1 and put result in xmm1.
  VEX.NDS.256.66.0F38.W1 9C /r VFNMADD132PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and add to ymm2 and put result in ymm1.
  VEX.NDS.256.66.0F38.W1 AC /r VFNMADD213PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/mem and put result in ymm1.
  VEX.NDS.256.66.0F38.W1 BC /r VFNMADD231PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and add to ymm1 and put result in ymm1.
  EVEX.NDS.128.66.0F38.W1 9C /r VFNMADD132PD xmm0 {k1}{z}, xmm1, xmm2/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, negate the multiplication result and add to xmm2 and put result in xmm1.
  EVEX.NDS.128.66.0F38.W1 AC /r VFNMADD213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/m128/m64bcst and put result in xmm1.
  EVEX.NDS.128.66.0F38.W1 BC /r VFNMADD231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, negate the multiplication result and add to xmm1 and put result in xmm1.
  EVEX.NDS.256.66.0F38.W1 9C /r VFNMADD132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, negate the multiplication result and add to ymm2 and put result in ymm1.
  EVEX.NDS.256.66.0F38.W1 AC /r VFNMADD213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/m256/m64bcst and put result in ymm1.
  EVEX.NDS.256.66.0F38.W1 BC /r VFNMADD231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, negate the multiplication result and add to ymm1 and put result in ymm1.
  EVEX.NDS.512.66.0F38.W1 9C /r VFNMADD132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, negate the multiplication result and add to zmm2 and put result in zmm1.
  EVEX.NDS.512.66.0F38.W1 AC /r VFNMADD213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm2, negate the multiplication result and add to zmm3/m512/m64bcst and put result in zmm1.
  EVEX.NDS.512.66.0F38.W1 BC /r VFNMADD231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, negate the multiplication result and add to zmm1 and put result in zmm1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFNMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source operand to the two, four or eight packed double-precision floating-point values in the third source operand, adds the negated infinite precision intermediate result to the two, four or eight packed double-precision floating- point values in the second source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  VFNMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source operand to the two, four or eight packed double-precision floating-point values in the first source operand, adds the negated infinite precision intermediate result to the two, four or eight packed double-precision floating- point values in the third source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  VFNMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source to the two, four or eight packed double-precision floating-point values in the third source operand, the negated infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  
  

  VFNMADD132PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(-(DEST[n+63:n]*SRC3[n+63:n]) + SRC2[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFNMADD213PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(-(SRC2[n+63:n]*DEST[n+63:n]) + SRC3[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFNMADD231PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR(-(SRC2[n+63:n]*SRC3[n+63:n]) + DEST[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) + SRC2[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) + SRC2[i+63:i]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) + SRC2[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[63:0]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) + DEST[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) + DEST[i+63:i]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) + DEST[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFNMADDxxxPD m512d _mm512_fnmadd_pd( m512d a, m512d b, m512d c); VFNMADDxxxPD m512d _mm512_fnmadd_round_pd( m512d a, m512d b, m512d c, int r);

  VFNMADDxxxPD m512d _mm512_mask_fnmadd_pd( m512d a, mmask8 k, m512d b, m512d c); VFNMADDxxxPD m512d _mm512_maskz_fnmadd_pd( mmask8 k, m512d a, m512d b, m512d c); VFNMADDxxxPD m512d _mm512_mask3_fnmadd_pd( m512d a, m512d b, m512d c, mmask8 k); VFNMADDxxxPD m512d _mm512_mask_fnmadd_round_pd( m512d a, mmask8 k, m512d b, m512d c, int r); VFNMADDxxxPD m512d _mm512_maskz_fnmadd_round_pd( mmask8 k, m512d a, m512d b, m512d c, int r); VFNMADDxxxPD m512d _mm512_mask3_fnmadd_round_pd( m512d a, m512d b, m512d c, mmask8 k, int r); VFNMADDxxxPD m256d _mm256_mask_fnmadd_pd( m256d a, mmask8 k, m256d b, m256d c); VFNMADDxxxPD m256d _mm256_maskz_fnmadd_pd( mmask8 k, m256d a, m256d b, m256d c); VFNMADDxxxPD m256d _mm256_mask3_fnmadd_pd( m256d a, m256d b, m256d c, mmask8 k); VFNMADDxxxPD m128d _mm_mask_fnmadd_pd( m128d a, mmask8 k, m128d b, m128d c);

  VFNMADDxxxPD m128d _mm_maskz_fnmadd_pd( mmask8 k, m128d a, m128d b, m128d c); VFNMADDxxxPD m128d _mm_mask3_fnmadd_pd( m128d a, m128d b, m128d c, mmask8 k); VFNMADDxxxPD m128d _mm_fnmadd_pd ( m128d a, m128d b, m128d c);

  VFNMADDxxxPD m256d _mm256_fnmadd_pd ( m256d a, m256d b, m256d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.NDS.128.66.0F38.W0 9C /r VFNMADD132PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and add to xmm2 and put result in xmm1.
  VEX.NDS.128.66.0F38.W0 AC /r VFNMADD213PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/mem and put result in xmm1.
  VEX.NDS.128.66.0F38.W0 BC /r VFNMADD231PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and add to xmm1 and put result in xmm1.
  VEX.NDS.256.66.0F38.W0 9C /r VFNMADD132PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and add to ymm2 and put result in ymm1.
  VEX.NDS.256.66.0F38.W0 AC /r VFNMADD213PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/mem and put result in ymm1.
  VEX.NDS.256.66.0F38.0 BC /r VFNMADD231PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and add to ymm1 and put result in ymm1.
  EVEX.NDS.128.66.0F38.W0 9C /r VFNMADD132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, negate the multiplication result and add to xmm2 and put result in xmm1.
  EVEX.NDS.128.66.0F38.W0 AC /r VFNMADD213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/m128/m32bcst and put result in xmm1.
  EVEX.NDS.128.66.0F38.W0 BC /r VFNMADD231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, negate the multiplication result and add to xmm1 and put result in xmm1.
  EVEX.NDS.256.66.0F38.W0 9C /r VFNMADD132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, negate the multiplication result and add to ymm2 and put result in ymm1.
  EVEX.NDS.256.66.0F38.W0 AC /r VFNMADD213PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/m256/m32bcst and put result in ymm1.
  EVEX.NDS.256.66.0F38.W0 BC /r VFNMADD231PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, negate the multiplication result and add to ymm1 and put result in ymm1.
  EVEX.NDS.512.66.0F38.W0 9C /r VFNMADD132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, negate the multiplication result and add to zmm2 and put result in zmm1.
  EVEX.NDS.512.66.0F38.W0 AC /r VFNMADD213PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm2, negate the multiplication result and add to zmm3/m512/m32bcst and put result in zmm1.
  EVEX.NDS.512.66.0F38.W0 BC /r VFNMADD231PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, negate the multiplication result and add to zmm1 and put result in zmm1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFNMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first source operand to the four, eight or sixteen packed single-precision floating-point values in the third source operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci- sion floating-point values in the second source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  VFNMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the four, eight or sixteen packed single-precision floating-point values in the first source operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci- sion floating-point values in the third source operand, performs rounding and stores the resulting the four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  VFNMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the four, eight or sixteen packed single-precision floating-point values in the third source operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci- sion floating-point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFNMADD132PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(- (DEST[n+31:n]*SRC3[n+31:n]) + SRC2[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFNMADD213PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(- (SRC2[n+31:n]*DEST[n+31:n]) + SRC3[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFNMADD231PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR(- (SRC2[n+31:n]*SRC3[n+31:n]) + DEST[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) + SRC2[i+31:i]) ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i]) FI;

  
  

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[31:0])

  
  

  ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) + DEST[i+31:i]) ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFNMADDxxxPS m512 _mm512_fnmadd_ps( m512 a, m512 b, m512 c); VFNMADDxxxPS m512 _mm512_fnmadd_round_ps( m512 a, m512 b, m512 c, int r);

  VFNMADDxxxPS m512 _mm512_mask_fnmadd_ps( m512 a, mmask16 k, m512 b, m512 c); VFNMADDxxxPS m512 _mm512_maskz_fnmadd_ps( mmask16 k, m512 a, m512 b, m512 c); VFNMADDxxxPS m512 _mm512_mask3_fnmadd_ps( m512 a, m512 b, m512 c, mmask16 k); VFNMADDxxxPS m512 _mm512_mask_fnmadd_round_ps( m512 a, mmask16 k, m512 b, m512 c, int r); VFNMADDxxxPS m512 _mm512_maskz_fnmadd_round_ps( mmask16 k, m512 a, m512 b, m512 c, int r); VFNMADDxxxPS m512 _mm512_mask3_fnmadd_round_ps( m512 a, m512 b, m512 c, mmask16 k, int r); VFNMADDxxxPS m256 _mm256_mask_fnmadd_ps( m256 a, mmask8 k, m256 b, m256 c); VFNMADDxxxPS m256 _mm256_maskz_fnmadd_ps( mmask8 k, m256 a, m256 b, m256 c); VFNMADDxxxPS m256 _mm256_mask3_fnmadd_ps( m256 a, m256 b, m256 c, mmask8 k); VFNMADDxxxPS m128 _mm_mask_fnmadd_ps( m128 a, mmask8 k, m128 b, m128 c);

  VFNMADDxxxPS m128 _mm_maskz_fnmadd_ps( mmask8 k, m128 a, m128 b, m128 c); VFNMADDxxxPS m128 _mm_mask3_fnmadd_ps( m128 a, m128 b, m128 c, mmask8 k); VFNMADDxxxPS m128 _mm_fnmadd_ps ( m128 a, m128 b, m128 c);

  VFNMADDxxxPS m256 _mm256_fnmadd_ps ( m256 a, m256 b, m256 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.LIG.66.0F38.W1 9D /r VFNMADD132SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm1 and xmm3/mem, negate the multiplication result and add to xmm2 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W1 AD /r VFNMADD213SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/mem and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W1 BD /r VFNMADD231SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm2 and xmm3/mem, negate the multiplication result and add to xmm1 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 9D /r VFNMADD132SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, negate the multiplication result and add to xmm2 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 AD /r VFNMADD213SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/m64 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 BD /r VFNMADD231SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, negate the multiplication result and add to xmm1 and put result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFNMADD132SD: Multiplies the low packed double-precision floating-point value from the first source operand to the low packed double-precision floating-point value in the third source operand, adds the negated infinite preci- sion intermediate result to the low packed double-precision floating-point values in the second source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VFNMADD213SD: Multiplies the low packed double-precision floating-point value from the second source operand to the low packed double-precision floating-point value in the first source operand, adds the negated infinite preci- sion intermediate result to the low packed double-precision floating-point value in the third source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VFNMADD231SD: Multiplies the low packed double-precision floating-point value from the second source to the low packed double-precision floating-point value in the third source operand, adds the negated infinite precision inter- mediate result to the low packed double-precision floating-point value in the first source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

  
  

  
  

  EVEX encoded version: The low quadword element of the destination is updated according to the writemask.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFNMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(-(DEST[63:0]*SRC3[63:0]) + SRC2[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  VFNMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(-(SRC2[63:0]*DEST[63:0]) + SRC3[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  
  

  VFNMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) + DEST[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  VFNMADD132SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) + SRC2[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  VFNMADD213SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) + SRC3[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  VFNMADD231SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) + DEST[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFNMADDxxxSD m128d _mm_fnmadd_round_sd( m128d a, m128d b, m128d c, int r); VFNMADDxxxSD m128d _mm_mask_fnmadd_sd( m128d a, mmask8 k, m128d b, m128d c); VFNMADDxxxSD m128d _mm_maskz_fnmadd_sd( mmask8 k, m128d a, m128d b, m128d c); VFNMADDxxxSD m128d _mm_mask3_fnmadd_sd( m128d a, m128d b, m128d c, mmask8 k);

  VFNMADDxxxSD m128d _mm_mask_fnmadd_round_sd( m128d a, mmask8 k, m128d b, m128d c, int r); VFNMADDxxxSD m128d _mm_maskz_fnmadd_round_sd( mmask8 k, m128d a, m128d b, m128d c, int r); VFNMADDxxxSD m128d _mm_mask3_fnmadd_round_sd( m128d a, m128d b, m128d c, mmask8 k, int r); VFNMADDxxxSD m128d _mm_fnmadd_sd ( m128d a, m128d b, m128d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 3. EVEX-encoded instructions, see Exceptions Type E3.

  
  

  VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.LIG.66.0F38.W0 9D /r VFNMADD132SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and add to xmm2 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W0 AD /r VFNMADD213SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/m32 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W0 BD /r VFNMADD231SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and add to xmm1 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 9D /r VFNMADD132SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and add to xmm2 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 AD /r VFNMADD213SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/m32 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 BD /r VFNMADD231SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and add to xmm1 and put result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFNMADD132SS: Multiplies the low packed single-precision floating-point value from the first source operand to the low packed single-precision floating-point value in the third source operand, adds the negated infinite precision intermediate result to the low packed single-precision floating-point value in the second source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VFNMADD213SS: Multiplies the low packed single-precision floating-point value from the second source operand to the low packed single-precision floating-point value in the first source operand, adds the negated infinite precision intermediate result to the low packed single-precision floating-point value in the third source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VFNMADD231SS: Multiplies the low packed single-precision floating-point value from the second source operand to the low packed single-precision floating-point value in the third source operand, adds the negated infinite preci- sion intermediate result to the low packed single-precision floating-point value in the first source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

  
  

  
  

  EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  Operation

  In the operations below, “*” and “+” symbols represent multiplication and addition with infinite precision inputs and outputs (no rounding).

  
  

  VFNMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(-(DEST[31:0]*SRC3[31:0]) + SRC2[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  VFNMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(-(SRC2[31:0]*DEST[31:0]) + SRC3[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  
  

  VFNMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) + DEST[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  VFNMADD132SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) + SRC2[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  VFNMADD213SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) + SRC3[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  VFNMADD231SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) + DEST[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFNMADDxxxSS m128 _mm_fnmadd_round_ss( m128 a, m128 b, m128 c, int r); VFNMADDxxxSS m128 _mm_mask_fnmadd_ss( m128 a, mmask8 k, m128 b, m128 c); VFNMADDxxxSS m128 _mm_maskz_fnmadd_ss( mmask8 k, m128 a, m128 b, m128 c); VFNMADDxxxSS m128 _mm_mask3_fnmadd_ss( m128 a, m128 b, m128 c, mmask8 k);

  VFNMADDxxxSS m128 _mm_mask_fnmadd_round_ss( m128 a, mmask8 k, m128 b, m128 c, int r); VFNMADDxxxSS m128 _mm_maskz_fnmadd_round_ss( mmask8 k, m128 a, m128 b, m128 c, int r); VFNMADDxxxSS m128 _mm_mask3_fnmadd_round_ss( m128 a, m128 b, m128 c, mmask8 k, int r); VFNMADDxxxSS m128 _mm_fnmadd_ss ( m128 a, m128 b, m128 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 3. EVEX-encoded instructions, see Exceptions Type E3.

  
  

  VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.NDS.128.66.0F38.W1 9E /r VFNMSUB132PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and subtract xmm2 and put result in xmm1.
  VEX.NDS.128.66.0F38.W1 AE /r VFNMSUB213PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/mem and put result in xmm1.
  VEX.NDS.128.66.0F38.W1 BE /r VFNMSUB231PD xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and subtract xmm1 and put result in xmm1.
  VEX.NDS.256.66.0F38.W1 9E /r VFNMSUB132PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and subtract ymm2 and put result in ymm1.
  VEX.NDS.256.66.0F38.W1 AE /r VFNMSUB213PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/mem and put result in ymm1.
  VEX.NDS.256.66.0F38.W1 BE /r VFNMSUB231PD ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and subtract ymm1 and put result in ymm1.
  EVEX.NDS.128.66.0F38.W1 9E /r VFNMSUB132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, negate the multiplication result and subtract xmm2 and put result in xmm1.
  EVEX.NDS.128.66.0F38.W1 AE /r VFNMSUB213PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m128/m64bcst and put result in xmm1.
  EVEX.NDS.128.66.0F38.W1 BE /r VFNMSUB231PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, negate the multiplication result and subtract xmm1 and put result in xmm1.
  EVEX.NDS.256.66.0F38.W1 9E /r VFNMSUB132PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, negate the multiplication result and subtract ymm2 and put result in ymm1.
  EVEX.NDS.256.66.0F38.W1 AE /r VFNMSUB213PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/m256/m64bcst and put result in ymm1.
  EVEX.NDS.256.66.0F38.W1 BE /r VFNMSUB231PD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst	B	V/V	AVX512VL AVX512F	Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, negate the multiplication result and subtract ymm1 and put result in ymm1.
  EVEX.NDS.512.66.0F38.W1 9E /r VFNMSUB132PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, negate the multiplication result and subtract zmm2 and put result in zmm1.
  EVEX.NDS.512.66.0F38.W1 AE /r VFNMSUB213PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm1 and zmm2, negate the multiplication result and subtract zmm3/m512/m64bcst and put result in zmm1.
  EVEX.NDS.512.66.0F38.W1 BE /r VFNMSUB231PD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst{er}	B	V/V	AVX512F	Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, negate the multiplication result and subtract zmm1 and put result in zmm1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFNMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source operand to the two, four or eight packed double-precision floating-point values in the third source operand. From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floating-point values in the second source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  VFNMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source operand to the two, four or eight packed double-precision floating-point values in the first source operand. From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floating-point values in the third source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  VFNMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second source to the two, four or eight packed double-precision floating-point values in the third source operand. From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floating- point values in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFNMSUB132PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR( - (DEST[n+63:n]*SRC3[n+63:n]) - SRC2[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFNMSUB213PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR( - (SRC2[n+63:n]*DEST[n+63:n]) - SRC3[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFNMSUB231PD DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  64*i;

  DEST[n+63:n]  RoundFPControl_MXCSR( - (SRC2[n+63:n]*SRC3[n+63:n]) - DEST[n+63:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) - SRC2[i+63:i]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[63:0]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN DEST[i+63:i] 

  RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) - DEST[i+63:i]) ELSE

  DEST[i+63:i] 

  RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+63:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+63:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFNMSUBxxxPD m512d _mm512_fnmsub_pd( m512d a, m512d b, m512d c); VFNMSUBxxxPD m512d _mm512_fnmsub_round_pd( m512d a, m512d b, m512d c, int r);

  VFNMSUBxxxPD m512d _mm512_mask_fnmsub_pd( m512d a, mmask8 k, m512d b, m512d c); VFNMSUBxxxPD m512d _mm512_maskz_fnmsub_pd( mmask8 k, m512d a, m512d b, m512d c); VFNMSUBxxxPD m512d _mm512_mask3_fnmsub_pd( m512d a, m512d b, m512d c, mmask8 k); VFNMSUBxxxPD m512d _mm512_mask_fnmsub_round_pd( m512d a, mmask8 k, m512d b, m512d c, int r); VFNMSUBxxxPD m512d _mm512_maskz_fnmsub_round_pd( mmask8 k, m512d a, m512d b, m512d c, int r); VFNMSUBxxxPD m512d _mm512_mask3_fnmsub_round_pd( m512d a, m512d b, m512d c, mmask8 k, int r); VFNMSUBxxxPD m256d _mm256_mask_fnmsub_pd( m256d a, mmask8 k, m256d b, m256d c); VFNMSUBxxxPD m256d _mm256_maskz_fnmsub_pd( mmask8 k, m256d a, m256d b, m256d c); VFNMSUBxxxPD m256d _mm256_mask3_fnmsub_pd( m256d a, m256d b, m256d c, mmask8 k); VFNMSUBxxxPD m128d _mm_mask_fnmsub_pd( m128d a, mmask8 k, m128d b, m128d c);

  VFNMSUBxxxPD m128d _mm_maskz_fnmsub_pd( mmask8 k, m128d a, m128d b, m128d c); VFNMSUBxxxPD m128d _mm_mask3_fnmsub_pd( m128d a, m128d b, m128d c, mmask8 k); VFNMSUBxxxPD m128d _mm_fnmsub_pd ( m128d a, m128d b, m128d c);

  VFNMSUBxxxPD m256d _mm256_fnmsub_pd ( m256d a, m256d b, m256d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.NDS.128.66.0F38.W0 9E /r VFNMSUB132PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and subtract xmm2 and put result in xmm1.
  VEX.NDS.128.66.0F38.W0 AE /r VFNMSUB213PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/mem and put result in xmm1.
  VEX.NDS.128.66.0F38.W0 BE /r VFNMSUB231PS xmm1, xmm2, xmm3/m128	A	V/V	FMA	Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and subtract xmm1 and put result in xmm1.
  VEX.NDS.256.66.0F38.W0 9E /r VFNMSUB132PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and subtract ymm2 and put result in ymm1.
  VEX.NDS.256.66.0F38.W0 AE /r VFNMSUB213PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/mem and put result in ymm1.
  VEX.NDS.256.66.0F38.0 BE /r VFNMSUB231PS ymm1, ymm2, ymm3/m256	A	V/V	FMA	Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and subtract ymm1 and put result in ymm1.
  EVEX.NDS.128.66.0F38.W0 9E /r VFNMSUB132PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, negate the multiplication result and subtract xmm2 and put result in xmm1.
  EVEX.NDS.128.66.0F38.W0 AE /r VFNMSUB213PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m128/m32bcst and put result in xmm1.
  EVEX.NDS.128.66.0F38.W0 BE /r VFNMSUB231PS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, negate the multiplication result subtract add to xmm1 and put result in xmm1.
  EVEX.NDS.256.66.0F38.W0 9E /r VFNMSUB132PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, negate the multiplication result and subtract ymm2 and put result in ymm1.
  EVEX.NDS.256.66.0F38.W0 AE /r VFNMSUB213PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/m256/m32bcst and put result in ymm1.
  EVEX.NDS.256.66.0F38.W0 BE /r VFNMSUB231PS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst	B	V/V	AVX512VL AVX512F	Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, negate the multiplication result subtract add to ymm1 and put result in ymm1.
  EVEX.NDS.512.66.0F38.W0 9E /r VFNMSUB132PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, negate the multiplication result and subtract zmm2 and put result in zmm1.
  EVEX.NDS.512.66.0F38.W0 AE /r VFNMSUB213PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm1 and zmm2, negate the multiplication result and subtract zmm3/m512/m32bcst and put result in zmm1.
  EVEX.NDS.512.66.0F38.W0 BE /r VFNMSUB231PS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er}	B	V/V	AVX512F	Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, negate the multiplication result subtract add to zmm1 and put result in zmm1.

  
  

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Full	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFNMSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first source operand to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single- precision floating-point values in the second source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  VFNMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source operand to the four, eight or sixteen packed single-precision floating-point values in the first source operand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single- precision floating-point values in the third source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  VFNMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second source to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single-precision floating- point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed single-precision floating-point values to the destination operand (first source operand).

  EVEX encoded versions: The destination operand (also first source operand) and the second source operand are ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca- tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition- ally updated with write mask k1.

  VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a YMM register or a 256-bit memory location and encoded in rm_field.

  VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination register are zeroed.

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFNMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR( - (DEST[n+31:n]*SRC3[n+31:n]) - SRC2[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  
  

  VFNMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR( - (SRC2[n+31:n]*DEST[n+31:n]) - SRC3[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFNMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)

  IF (VEX.128) THEN MAXNUM 2

  ELSEIF (VEX.256) MAXNUM  4

  FI

  For i = 0 to MAXNUM-1 {

  n  32*i;

  DEST[n+31:n]  RoundFPControl_MXCSR( - (SRC2[n+31:n]*SRC3[n+31:n]) - DEST[n+31:n])

  }

  IF (VEX.128) THEN DEST[MAXVL-1:128]  0

  ELSEIF (VEX.256) DEST[MAXVL-1:256]  0

  FI

  
  

  VFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) - SRC2[i+31:i]) ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[31:0]) ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  VFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)

  (KL, VL) = (4, 128), (8, 256), (16, 512) IF (VL = 512) AND (EVEX.b = 1)

  THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) - DEST[i+31:i]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  
  

  VFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  
  

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b = 1) THEN

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) - DEST[i+31:i]) ELSE

  DEST[i+31:i] 

  RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) - DEST[i+31:i]) FI;

  ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged*

  ELSE ; zeroing-masking

  DEST[i+31:i]  0

  FI

  FI;

  ENDFOR

  DEST[MAXVL-1:VL]  0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFNMSUBxxxPS m512 _mm512_fnmsub_ps( m512 a, m512 b, m512 c); VFNMSUBxxxPS m512 _mm512_fnmsub_round_ps( m512 a, m512 b, m512 c, int r);

  VFNMSUBxxxPS m512 _mm512_mask_fnmsub_ps( m512 a, mmask16 k, m512 b, m512 c); VFNMSUBxxxPS m512 _mm512_maskz_fnmsub_ps( mmask16 k, m512 a, m512 b, m512 c); VFNMSUBxxxPS m512 _mm512_mask3_fnmsub_ps( m512 a, m512 b, m512 c, mmask16 k); VFNMSUBxxxPS m512 _mm512_mask_fnmsub_round_ps( m512 a, mmask16 k, m512 b, m512 c, int r); VFNMSUBxxxPS m512 _mm512_maskz_fnmsub_round_ps( mmask16 k, m512 a, m512 b, m512 c, int r); VFNMSUBxxxPS m512 _mm512_mask3_fnmsub_round_ps( m512 a, m512 b, m512 c, mmask16 k, int r); VFNMSUBxxxPS m256 _mm256_mask_fnmsub_ps( m256 a, mmask8 k, m256 b, m256 c); VFNMSUBxxxPS m256 _mm256_maskz_fnmsub_ps( mmask8 k, m256 a, m256 b, m256 c); VFNMSUBxxxPS m256 _mm256_mask3_fnmsub_ps( m256 a, m256 b, m256 c, mmask8 k); VFNMSUBxxxPS m128 _mm_mask_fnmsub_ps( m128 a, mmask8 k, m128 b, m128 c);

  VFNMSUBxxxPS m128 _mm_maskz_fnmsub_ps( mmask8 k, m128 a, m128 b, m128 c); VFNMSUBxxxPS m128 _mm_mask3_fnmsub_ps( m128 a, m128 b, m128 c, mmask8 k); VFNMSUBxxxPS m128 _mm_fnmsub_ps ( m128 a, m128 b, m128 c);

  VFNMSUBxxxPS m256 _mm256_fnmsub_ps ( m256 a, m256 b, m256 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 2. EVEX-encoded instructions, see Exceptions Type E2.

  
  

  VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.LIG.66.0F38.W1 9F /r VFNMSUB132SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm1 and xmm3/mem, negate the multiplication result and subtract xmm2 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W1 AF /r VFNMSUB213SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/mem and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W1 BF /r VFNMSUB231SD xmm1, xmm2, xmm3/m64	A	V/V	FMA	Multiply scalar double-precision floating-point value from xmm2 and xmm3/mem, negate the multiplication result and subtract xmm1 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 9F /r VFNMSUB132SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, negate the multiplication result and subtract xmm2 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 AF /r VFNMSUB213SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m64 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W1 BF /r VFNMSUB231SD xmm1 {k1}{z}, xmm2, xmm3/m64{er}	B	V/V	AVX512F	Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, negate the multiplication result and subtract xmm1 and put result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFNMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to the low packed double-precision floating-point value in the third source operand. From negated infinite precision intermediate result, subtracts the low double-precision floating-point value in the second source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VFNMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand to the low packed double-precision floating-point value in the first source operand. From negated infinite precision intermediate result, subtracts the low double-precision floating-point value in the third source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VFNMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low packed double-precision floating-point value in the third source operand. From negated infinite precision interme- diate result, subtracts the low double-precision floating-point value in the first source operand, performs rounding and stores the resulting packed double-precision floating-point value to the destination operand (first source operand).

  VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

  
  

  
  

  EVEX encoded version: The low quadword element of the destination is updated according to the writemask.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFNMSUB132SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(-(DEST[63:0]*SRC3[63:0]) - SRC2[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  VFNMSUB213SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(-(SRC2[63:0]*DEST[63:0]) - SRC3[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  
  

  VFNMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[63:0]  RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) - DEST[63:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[63:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[63:0]  0

  FI;

  FI;

  DEST[127:64]  DEST[127:64] DEST[MAXVL-1:128]  0

  
  

  VFNMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) - SRC2[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  VFNMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) - SRC3[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  VFNMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)

  DEST[63:0] RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) - DEST[63:0]) DEST[127:64] DEST[127:64]

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFNMSUBxxxSD m128d _mm_fnmsub_round_sd( m128d a, m128d b, m128d c, int r); VFNMSUBxxxSD m128d _mm_mask_fnmsub_sd( m128d a, mmask8 k, m128d b, m128d c); VFNMSUBxxxSD m128d _mm_maskz_fnmsub_sd( mmask8 k, m128d a, m128d b, m128d c); VFNMSUBxxxSD m128d _mm_mask3_fnmsub_sd( m128d a, m128d b, m128d c, mmask8 k);

  VFNMSUBxxxSD m128d _mm_mask_fnmsub_round_sd( m128d a, mmask8 k, m128d b, m128d c, int r); VFNMSUBxxxSD m128d _mm_maskz_fnmsub_round_sd( mmask8 k, m128d a, m128d b, m128d c, int r); VFNMSUBxxxSD m128d _mm_mask3_fnmsub_round_sd( m128d a, m128d b, m128d c, mmask8 k, int r); VFNMSUBxxxSD m128d _mm_fnmsub_sd ( m128d a, m128d b, m128d c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 3. EVEX-encoded instructions, see Exceptions Type E3.

  
  

  VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  VEX.DDS.LIG.66.0F38.W0 9F /r VFNMSUB132SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and subtract xmm2 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W0 AF /r VFNMSUB213SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m32 and put result in xmm1.
  VEX.DDS.LIG.66.0F38.W0 BF /r VFNMSUB231SS xmm1, xmm2, xmm3/m32	A	V/V	FMA	Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and subtract xmm1 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 9F /r VFNMSUB132SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and subtract xmm2 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 AF /r VFNMSUB213SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m32 and put result in xmm1.
  EVEX.DDS.LIG.66.0F38.W0 BF /r VFNMSUB231SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}	B	V/V	AVX512F	Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and subtract xmm1 and put result in xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	NA	ModRM:reg (r, w)	VEX.vvvv (r)	ModRM:r/m (r)	NA
  B	Tuple1 Scalar	ModRM:reg (r, w)	EVEX.vvvv (r)	ModRM:r/m (r)	NA

  Description

  VFNMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to the low packed single-precision floating-point value in the third source operand. From negated infinite precision intermediate result, the low single-precision floating-point value in the second source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VFNMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to the low packed single-precision floating-point value in the first source operand. From negated infinite precision intermediate result, the low single-precision floating-point value in the third source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VFNMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low packed single-precision floating-point value in the third source operand. From negated infinite precision interme- diate result, the low single-precision floating-point value in the first source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).

  VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.

  EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.

  Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.

  
  

  
  

  Operation

  In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no rounding).

  
  

  VFNMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(-(DEST[31:0]*SRC3[31:0]) - SRC2[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  VFNMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(-(SRC2[31:0]*DEST[31:0]) - SRC3[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  
  

  VFNMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)

  IF (EVEX.b = 1) and SRC3 *is a register* THEN

  SET_RM(EVEX.RC);

  ELSE

  SET_RM(MXCSR.RM);

  FI;

  IF k1[0] or *no writemask*

  THEN DEST[31:0]  RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) - DEST[31:0]) ELSE

  IF *merging-masking* ; merging-masking THEN *DEST[31:0] remains unchanged*

  ELSE ; zeroing-masking

  THEN DEST[31:0]  0

  FI;

  FI;

  DEST[127:32]  DEST[127:32] DEST[MAXVL-1:128]  0

  
  

  VFNMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) - SRC2[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  VFNMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) - SRC3[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  VFNMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)

  DEST[31:0] RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) - DEST[31:0]) DEST[127:32] DEST[127:32]

  DEST[MAXVL-1:128] 0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFNMSUBxxxSS m128 _mm_fnmsub_round_ss( m128 a, m128 b, m128 c, int r); VFNMSUBxxxSS m128 _mm_mask_fnmsub_ss( m128 a, mmask8 k, m128 b, m128 c); VFNMSUBxxxSS m128 _mm_maskz_fnmsub_ss( mmask8 k, m128 a, m128 b, m128 c); VFNMSUBxxxSS m128 _mm_mask3_fnmsub_ss( m128 a, m128 b, m128 c, mmask8 k);

  VFNMSUBxxxSS m128 _mm_mask_fnmsub_round_ss( m128 a, mmask8 k, m128 b, m128 c, int r); VFNMSUBxxxSS m128 _mm_maskz_fnmsub_round_ss( mmask8 k, m128 a, m128 b, m128 c, int r); VFNMSUBxxxSS m128 _mm_mask3_fnmsub_round_ss( m128 a, m128 b, m128 c, mmask8 k, int r); VFNMSUBxxxSS m128 _mm_fnmsub_ss ( m128 a, m128 b, m128 c);

  
  

  SIMD Floating-Point Exceptions

  Overflow, Underflow, Invalid, Precision, Denormal

  
  

  Other Exceptions

  VEX-encoded instructions, see Exceptions Type 3. EVEX-encoded instructions, see Exceptions Type E3.

  
  

  VFPCLASSPD—Tests Types Of a Packed Float64 Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.128.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, xmm2/m128/m64bcst, imm8	A	V/V	AVX512VL AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
  EVEX.256.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, ymm2/m256/m64bcst, imm8	A	V/V	AVX512VL AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
  EVEX.512.66.0F3A.W1 66 /r ib VFPCLASSPD k2 {k1}, zmm2/m512/m64bcst, imm8	A	V/V	AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Full	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

  Description

  The FPCLASSPD instruction checks the packed double precision floating point values for special categories, speci- fied by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result of each element is written to the corre- sponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:8/4/2] of the destination are cleared.

  The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category is listed in Table 5-4.

  
  

  

  7 6 5 4 3 2 1 0

  
  

  SNaN

  Neg. Finite

  Denormal

  Neg. INF

  +INF

  Neg. 0

  +0

  QNaN

  
  

  Figure 5-13. Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SS

  
  

  Table 5-4. Classifier Operations for VFPCLASSPD/SD/PS/SS

  Bits	Imm8[0]	Imm8[1]	Imm8[2]	Imm8[3]	Imm8[4]	Imm8[5]	Imm8[6]	Imm8[7]
  Category	QNAN	PosZero	NegZero	PosINF	NegINF	Denormal	Negative	SNAN
  Classifier	Checks for QNaN	Checks for +0	Checks for - 0	Checks for +INF	Checks for - INF	Checks for Denormal	Checks for Negative finite	Checks for SNaN

  The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.

  EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

  
  

  
  

  Operation

  CheckFPClassDP (tsrc[63:0], imm8[7:0]){

  
  

  //* Start checking the source operand for special type *// NegNum  tsrc[63];

  IF (tsrc[62:52]=07FFh) Then ExpAllOnes  1; FI; IF (tsrc[62:52]=0h) Then ExpAllZeros  1;

  IF (ExpAllZeros AND MXCSR.DAZ) Then MantAllZeros  1;

  ELSIF (tsrc[51:0]=0h) Then

  MantAllZeros  1;

  FI;

  ZeroNumber  ExpAllZeros AND MantAllZeros SignalingBit  tsrc[51];

  
  

  sNaN_res  ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN qNaN_res  ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN Pzero_res  NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0 Nzero_res  NegNum AND ExpAllZeros AND MantAllZeros; // -0

  PInf_res  NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf NInf_res  NegNum AND ExpAllOnes AND MantAllZeros; // -Inf Denorm_res  ExpAllZeros AND NOT(MantAllZeros); // denorm

  FinNeg_res  NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite

  
  

  bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR

  ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );

  Return bResult;

  } //* end of CheckFPClassDP() *//

  
  

  VFPCLASSPD (EVEX Encoded versions)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  FOR j  0 TO KL-1

  i  j * 64

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b == 1) AND (SRC *is memory*) THEN

  DEST[j]  CheckFPClassDP(SRC1[63:0], imm8[7:0]); ELSE

  DEST[j]  CheckFPClassDP(SRC1[i+63:i], imm8[7:0]);

  
  

  FI;

  FI;

  ELSE DEST[j]  0 ; zeroing-masking only

  ENDFOR

  DEST[MAX_KL-1:KL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFPCLASSPD mmask8 _mm512_fpclass_pd_mask( m512d a, int c);

  VFPCLASSPD mmask8 _mm512_mask_fpclass_pd_mask( mmask8 m, m512d a, int c) VFPCLASSPD mmask8 _mm256_fpclass_pd_mask( m256d a, int c)

  VFPCLASSPD mmask8 _mm256_mask_fpclass_pd_mask( mmask8 m, m256d a, int c) VFPCLASSPD mmask8 _mm_fpclass_pd_mask( m128d a, int c)

  VFPCLASSPD mmask8 _mm_mask_fpclass_pd_mask( mmask8 m, m128d a, int c)

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type E4

  #UD If EVEX.vvvv != 1111B.

  
  

  VFPCLASSPS—Tests Types Of a Packed Float32 Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.128.66.0F3A.W0 66 /r ib VFPCLASSPS k2 {k1}, xmm2/m128/m32bcst, imm8	A	V/V	AVX512VL AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
  EVEX.256.66.0F3A.W0 66 /r ib VFPCLASSPS k2 {k1}, ymm2/m256/m32bcst, imm8	A	V/V	AVX512VL AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.
  EVEX.512.66.0F3A.W0 66 /r ib VFPCLASSPS k2 {k1}, zmm2/m512/m32bcst, imm8	A	V/V	AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Full	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

  Description

  The FPCLASSPS instruction checks the packed single-precision floating point values for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result of each element is written to the corre- sponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:16/8/4] of the destination are cleared.

  The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category is listed in Table 5-4.

  The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location.

  EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

  
  

  Operation

  CheckFPClassSP (tsrc[31:0], imm8[7:0]){

  
  

  //* Start checking the source operand for special type *// NegNum  tsrc[31];

  IF (tsrc[30:23]=0FFh) Then ExpAllOnes  1; FI; IF (tsrc[30:23]=0h) Then ExpAllZeros  1;

  IF (ExpAllZeros AND MXCSR.DAZ) Then MantAllZeros  1;

  ELSIF (tsrc[22:0]=0h) Then

  MantAllZeros  1;

  FI;

  ZeroNumber= ExpAllZeros AND MantAllZeros SignalingBit= tsrc[22];

  
  

  sNaN_res  ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN qNaN_res  ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN Pzero_res  NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0

  
  

  
  

  Nzero_res  NegNum AND ExpAllZeros AND MantAllZeros; // -0 PInf_res  NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf NInf_res  NegNum AND ExpAllOnes AND MantAllZeros; // -Inf Denorm_res  ExpAllZeros AND NOT(MantAllZeros); // denorm

  FinNeg_res  NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite

  
  

  bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR

  ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );

  Return bResult;

  } //* end of CheckSPClassSP() *//

  
  

  VFPCLASSPS (EVEX encoded versions)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  FOR j  0 TO KL-1

  i  j * 32

  IF k1[j] OR *no writemask* THEN

  IF (EVEX.b == 1) AND (SRC *is memory*) THEN

  DEST[j]  CheckFPClassDP(SRC1[31:0], imm8[7:0]); ELSE

  DEST[j]  CheckFPClassDP(SRC1[i+31:i], imm8[7:0]);

  
  

  FI;

  FI;

  ELSE DEST[j]  0 ; zeroing-masking only

  ENDFOR

  DEST[MAX_KL-1:KL]  0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFPCLASSPS mmask16 _mm512_fpclass_ps_mask( m512 a, int c);

  VFPCLASSPS mmask16 _mm512_mask_fpclass_ps_mask( mmask16 m, m512 a, int c) VFPCLASSPS mmask8 _mm256_fpclass_ps_mask( m256 a, int c)

  VFPCLASSPS mmask8 _mm256_mask_fpclass_ps_mask( mmask8 m, m256 a, int c) VFPCLASSPS mmask8 _mm_fpclass_ps_mask( m128 a, int c)

  VFPCLASSPS mmask8 _mm_mask_fpclass_ps_mask( mmask8 m, m128 a, int c)

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type E4

  #UD If EVEX.vvvv != 1111B.

  
  

  VFPCLASSSD—Tests Types Of a Scalar Float64 Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.LIG.66.0F3A.W1 67 /r ib VFPCLASSSD k2 {k1}, xmm2/m64, imm8	A	V/V	AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Tuple1 Scalar	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

  Description

  The FPCLASSSD instruction checks the low double precision floating point value in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the low bit in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.

  The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category is listed in Table 5-4.

  EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

  
  

  Operation

  CheckFPClassDP (tsrc[63:0], imm8[7:0]){

  
  

  NegNum  tsrc[63];

  IF (tsrc[62:52]=07FFh) Then ExpAllOnes  1; FI; IF (tsrc[62:52]=0h) Then ExpAllZeros  1;

  IF (ExpAllZeros AND MXCSR.DAZ) Then MantAllZeros  1;

  ELSIF (tsrc[51:0]=0h) Then

  MantAllZeros  1;

  FI;

  ZeroNumber  ExpAllZeros AND MantAllZeros SignalingBit  tsrc[51];

  
  

  sNaN_res  ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN qNaN_res  ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN Pzero_res  NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0 Nzero_res  NegNum AND ExpAllZeros AND MantAllZeros; // -0

  PInf_res  NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf NInf_res  NegNum AND ExpAllOnes AND MantAllZeros; // -Inf Denorm_res  ExpAllZeros AND NOT(MantAllZeros); // denorm

  FinNeg_res  NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite

  
  

  bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR

  ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );

  Return bResult;

  } //* end of CheckFPClassDP() *//

  
  

  VFPCLASSSD—Tests Types Of a Scalar Float64 Values Vol. 2C 5-241

  
  

  
  

  VFPCLASSSD (EVEX encoded version)

  IF k1[0] OR *no writemask* THEN DEST[0] 

  CheckFPClassDP(SRC1[63:0], imm8[7:0])

  ELSE DEST[0]  0 ; zeroing-masking only

  FI;

  DEST[MAX_KL-1:1]  0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFPCLASSSD mmask8 _mm_fpclass_sd_mask( m128d a, int c)

  VFPCLASSSD mmask8 _mm_mask_fpclass_sd_mask( mmask8 m, m128d a, int c)

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type E6

  #UD If EVEX.vvvv != 1111B.

  
  

  VFPCLASSSS—Tests Types Of a Scalar Float32 Values

  Opcode/ Instruction	Op / En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.LIG.66.0F3A.W0 67 /r VFPCLASSSS k2 {k1}, xmm2/m32, imm8	A	V/V	AVX512DQ	Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Tuple1 Scalar	ModRM:reg (w)	ModRM:r/m (r)	NA	NA

  Description

  The FPCLASSSS instruction checks the low single-precision floating point value in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the low bit in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.

  The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category is listed in Table 5-4.

  EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

  
  

  Operation

  CheckFPClassSP (tsrc[31:0], imm8[7:0]){

  
  

  //* Start checking the source operand for special type *// NegNum  tsrc[31];

  IF (tsrc[30:23]=0FFh) Then ExpAllOnes  1; FI; IF (tsrc[30:23]=0h) Then ExpAllZeros  1;

  IF (ExpAllZeros AND MXCSR.DAZ) Then MantAllZeros  1;

  ELSIF (tsrc[22:0]=0h) Then

  MantAllZeros  1;

  FI;

  ZeroNumber= ExpAllZeros AND MantAllZeros SignalingBit= tsrc[22];

  
  

  sNaN_res  ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN qNaN_res  ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN Pzero_res  NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0 Nzero_res  NegNum AND ExpAllZeros AND MantAllZeros; // -0

  PInf_res  NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf NInf_res  NegNum AND ExpAllOnes AND MantAllZeros; // -Inf Denorm_res  ExpAllZeros AND NOT(MantAllZeros); // denorm

  FinNeg_res  NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite

  
  

  bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR

  ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );

  Return bResult;

  
  

  VFPCLASSSS—Tests Types Of a Scalar Float32 Values Vol. 2C 5-243

  
  

  
  

  } //* end of CheckSPClassSP() *//

  
  

  VFPCLASSSS (EVEX encoded version)

  IF k1[0] OR *no writemask* THEN DEST[0] 

  CheckFPClassSP(SRC1[31:0], imm8[7:0])

  ELSE DEST[0]  0 ; zeroing-masking only

  FI;

  DEST[MAX_KL-1:1]  0

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VFPCLASSSS mmask8 _mm_fpclass_ss_mask( m128 a, int c)

  VFPCLASSSS mmask8 _mm_mask_fpclass_ss_mask( mmask8 m, m128 a, int c)

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type E6

  #UD If EVEX.vvvv != 1111B.

  
  

  VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices

  Opcode/ Instruction	Op/ En	64/3 2-bit Mode	CPUID Feature Flag	Description
  VEX.DDS.128.66.0F38.W1 92 /r VGATHERDPD xmm1, vm32x, xmm2	RMV	V/V	AVX2	Using dword indices specified in vm32x, gather double-pre- cision FP values from memory conditioned on mask speci- fied by xmm2. Conditionally gathered elements are merged into xmm1.
  VEX.DDS.128.66.0F38.W1 93 /r VGATHERQPD xmm1, vm64x, xmm2	RMV	V/V	AVX2	Using qword indices specified in vm64x, gather double-pre- cision FP values from memory conditioned on mask speci- fied by xmm2. Conditionally gathered elements are merged into xmm1.
  VEX.DDS.256.66.0F38.W1 92 /r VGATHERDPD ymm1, vm32x, ymm2	RMV	V/V	AVX2	Using dword indices specified in vm32x, gather double-pre- cision FP values from memory conditioned on mask speci- fied by ymm2. Conditionally gathered elements are merged into ymm1.
  VEX.DDS.256.66.0F38.W1 93 /r VGATHERQPD ymm1, vm64y, ymm2	RMV	V/V	AVX2	Using qword indices specified in vm64y, gather double-pre- cision FP values from memory conditioned on mask speci- fied by ymm2. Conditionally gathered elements are merged into ymm1.

  
  

  Instruction Operand Encoding

  Op/En	Operand 1	Operand 2	Operand 3	Operand 4
  RMV	ModRM:reg (r,w)	BaseReg (R): VSIB:base, VectorReg(R): VSIB:index	VEX.vvvv (r, w)	NA

  
  

  Description

  The instruction conditionally loads up to 2 or 4 double-precision floating-point values from memory addresses specified by the memory operand (the second operand) and using qword indices. The memory operand uses the VSIB form of the SIB byte to specify a general purpose register operand as the common base, a vector register for an array of indices relative to the base and a constant scale factor.

  The mask operand (the third operand) specifies the conditional load operation from each memory address and the corresponding update of each data element of the destination operand (the first operand). Conditionality is speci- fied by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the corresponding element of the destination register is left unchanged. The width of data element in the destination register and mask register are identical. The entire mask register will be set to zero by this instruction unless the instruction causes an exception.

  Using dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 double- precision floating-point values from the VSIB addressing memory operand, and updates the destination register.

  This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination register and the mask operand are partially updated; those elements that have been gathered are placed into the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath- ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.

  If the data size and index size are different, part of the destination register and part of the mask register do not correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception before gathering any elements.

  
  

  
  

  VEX.128 version: The instruction will gather two double-precision floating-point values. For dword indices, only the lower two indices in the vector index register are used.

  VEX.256 version: The instruction will gather four double-precision floating-point values. For dword indices, only the lower four indices in the vector index register are used.

  Note that:

• If any pair of the index, mask, or destination registers are the same, this instruction results a #UD fault.

• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel- 64 memory-ordering model.

• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the conventional order.

• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to the left of a faulting one may be gathered before the fault is delivered. A given implementation of this instruction is repeatable - given the same input values and architectural state, the same set of elements to the left of the faulting one will be gathered.

• This instruction does not perform AC checks, and so will never deliver an AC fault.

• This instruction will cause a #UD if the address size attribute is 16-bit.

• This instruction will cause a #UD if the memory operand is encoded without the SIB byte.

• This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does is implementation specific, and some implementations may use loads larger than the data element size or load elements an indeterminate number of times.

• The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32- bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are ignored.

  
  

  
  

  Operation

  DEST  SRC1;

  BASE_ADDR: base register encoded in VSIB addressing; VINDEX: the vector index register encoded by VSIB addressing; SCALE: scale factor encoded by SIB:[7:6];

  DISP: optional 1, 4 byte displacement; MASK  SRC3;

  
  

  VGATHERDPD (VEX.128 version)

  FOR j 0 to 1 i  j * 64;

  IF MASK[63+i] THEN

  MASK[i +63:i]  FFFFFFFF_FFFFFFFFH; // extend from most significant bit ELSE

  MASK[i +63:i]  0;

  FI;

  ENDFOR

  FOR j 0 to 1 k  j * 32; i  j * 64;

  DATA_ADDR  BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP; IF MASK[63+i] THEN

  DEST[i +63:i]  FETCH_64BITS(DATA_ADDR); // a fault exits the instruction

  FI;

  MASK[i +63: i]  0; ENDFOR

  MASK[MAXVL-1:128]  0;

  DEST[MAXVL-1:128]  0;

  (non-masked elements of the mask register have the content of respective element cleared)

  
  

  VGATHERQPD (VEX.128 version)

  FOR j 0 to 1 i  j * 64;

  IF MASK[63+i] THEN

  MASK[i +63:i]  FFFFFFFF_FFFFFFFFH; // extend from most significant bit ELSE

  MASK[i +63:i]  0;

  FI;

  ENDFOR

  FOR j 0 to 1 i  j * 64;

  DATA_ADDR  BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP; IF MASK[63+i] THEN

  DEST[i +63:i]  FETCH_64BITS(DATA_ADDR); // a fault exits this instruction

  FI;

  MASK[i +63: i]  0; ENDFOR

  MASK[MAXVL-1:128]  0;

  DEST[MAXVL-1:128]  0;

  (non-masked elements of the mask register have the content of respective element cleared)

  
  

  
  

  VGATHERQPD (VEX.256 version)

  FOR j 0 to 3 i  j * 64;

  IF MASK[63+i] THEN

  MASK[i +63:i]  FFFFFFFF_FFFFFFFFH; // extend from most significant bit ELSE

  MASK[i +63:i]  0;

  FI;

  ENDFOR

  FOR j 0 to 3 i  j * 64;

  DATA_ADDR  BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP; IF MASK[63+i] THEN

  DEST[i +63:i]  FETCH_64BITS(DATA_ADDR); // a fault exits the instruction

  FI;

  MASK[i +63: i]  0; ENDFOR

  (non-masked elements of the mask register have the content of respective element cleared)

  
  

  VGATHERDPD (VEX.256 version)

  FOR j 0 to 3 i  j * 64;

  IF MASK[63+i] THEN

  MASK[i +63:i]  FFFFFFFF_FFFFFFFFH; // extend from most significant bit ELSE

  MASK[i +63:i]  0;

  FI;

  ENDFOR

  FOR j 0 to 3 k  j * 32; i  j * 64;

  DATA_ADDR  BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP; IF MASK[63+i] THEN

  DEST[i +63:i]  FETCH_64BITS(DATA_ADDR); // a fault exits the instruction

  FI;

  MASK[i +63:i]  0; ENDFOR

  (non-masked elements of the mask register have the content of respective element cleared)

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VGATHERDPD: m128d _mm_i32gather_pd (double const * base, m128i index, const int scale);

  VGATHERDPD: m128d _mm_mask_i32gather_pd ( m128d src, double const * base, m128i index, m128d mask, const int scale);

  VGATHERDPD: m256d _mm256_i32gather_pd (double const * base, m128i index, const int scale);

  VGATHERDPD: m256d _mm256_mask_i32gather_pd ( m256d src, double const * base, m128i index, m256d mask, const int scale);

  VGATHERQPD: m128d _mm_i64gather_pd (double const * base, m128i index, const int scale);

  VGATHERQPD: m128d _mm_mask_i64gather_pd ( m128d src, double const * base, m128i index, m128d mask, const int scale);

  VGATHERQPD: m256d _mm256_i64gather_pd (double const * base, m256i index, const int scale);

  VGATHERQPD: m256d _mm256_mask_i64gather_pd ( m256d src, double const * base, m256i index, m256d mask, const int scale);

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type 12.

  
  

  VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices

  Opcode/ Instruction	Op/ En	64/32 -bit Mode	CPUID Feature Flag	Description
  VEX.DDS.128.66.0F38.W0 92 /r VGATHERDPS xmm1, vm32x, xmm2	A	V/V	AVX2	Using dword indices specified in vm32x, gather single-preci- sion FP values from memory conditioned on mask specified by xmm2. Conditionally gathered elements are merged into xmm1.
  VEX.DDS.128.66.0F38.W0 93 /r VGATHERQPS xmm1, vm64x, xmm2	A	V/V	AVX2	Using qword indices specified in vm64x, gather single-preci- sion FP values from memory conditioned on mask specified by xmm2. Conditionally gathered elements are merged into xmm1.
  VEX.DDS.256.66.0F38.W0 92 /r VGATHERDPS ymm1, vm32y, ymm2	A	V/V	AVX2	Using dword indices specified in vm32y, gather single-preci- sion FP values from memory conditioned on mask specified by ymm2. Conditionally gathered elements are merged into ymm1.
  VEX.DDS.256.66.0F38.W0 93 /r VGATHERQPS xmm1, vm64y, xmm2	A	V/V	AVX2	Using qword indices specified in vm64y, gather single-preci- sion FP values from memory conditioned on mask specified by xmm2. Conditionally gathered elements are merged into xmm1.

  
  

  Instruction Operand Encoding

  Op/En	Operand 1	Operand 2	Operand 3	Operand 4
  A	ModRM:reg (r,w)	BaseReg (R): VSIB:base, VectorReg(R): VSIB:index	VEX.vvvv (r, w)	NA

  
  

  Description

  The instruction conditionally loads up to 4 or 8 single-precision floating-point values from memory addresses spec- ified by the memory operand (the second operand) and using dword indices. The memory operand uses the VSIB form of the SIB byte to specify a general purpose register operand as the common base, a vector register for an array of indices relative to the base and a constant scale factor.

  The mask operand (the third operand) specifies the conditional load operation from each memory address and the corresponding update of each data element of the destination operand (the first operand). Conditionality is speci- fied by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the corresponding element of the destination register is left unchanged. The width of data element in the destination register and mask register are identical. The entire mask register will be set to zero by this instruction unless the instruction causes an exception.

  Using qword indices, the instruction conditionally loads up to 2 or 4 single-precision floating-point values from the VSIB addressing memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits of the destination register are zero’ed with qword indices.

  This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination register and the mask operand are partially updated; those elements that have been gathered are placed into the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath- ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.

  If the data size and index size are different, part of the destination register and part of the mask register do not correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception before gathering any elements.

  
  

  
  

  VEX.128 version: For dword indices, the instruction will gather four single-precision floating-point values. For qword indices, the instruction will gather two values and zero the upper 64 bits of the destination.

  VEX.256 version: For dword indices, the instruction will gather eight single-precision floating-point values. For qword indices, the instruction will gather four values and zero the upper 128 bits of the destination.

  Note that:

• If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.

• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel- 64 memory-ordering model.

• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the conventional order.

• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to the left of a faulting one may be gathered before the fault is delivered. A given implementation of this instruction is repeatable - given the same input values and architectural state, the same set of elements to the left of the faulting one will be gathered.

• This instruction does not perform AC checks, and so will never deliver an AC fault.

• This instruction will cause a #UD if the address size attribute is 16-bit.

• This instruction will cause a #UD if the memory operand is encoded without the SIB byte.

• This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does is implementation specific, and some implementations may use loads larger than the data element size or load elements an indeterminate number of times.

• The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32- bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are ignored.

  
  

  Operation

  DEST  SRC1;

  BASE_ADDR: base register encoded in VSIB addressing; VINDEX: the vector index register encoded by VSIB addressing; SCALE: scale factor encoded by SIB:[7:6];

  DISP: optional 1, 4 byte displacement; MASK  SRC3;

  
  

  
  

  VGATHERDPS (VEX.128 version)

  FOR j 0 to 3 i  j * 32;

  IF MASK[31+i] THEN

  MASK[i +31:i]  FFFFFFFFH; // extend from most significant bit ELSE

  MASK[i +31:i]  0;

  FI;

  ENDFOR

  MASK[MAXVL-1:128]  0;

  FOR j 0 to 3 i  j * 32;

  DATA_ADDR  BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP; IF MASK[31+i] THEN

  DEST[i +31:i]  FETCH_32BITS(DATA_ADDR); // a fault exits the instruction

  FI;

  MASK[i +31:i]  0; ENDFOR

  DEST[MAXVL-1:128]  0;

  (non-masked elements of the mask register have the content of respective element cleared)

  
  

  VGATHERQPS (VEX.128 version)

  FOR j 0 to 3 i  j * 32;

  IF MASK[31+i] THEN

  MASK[i +31:i]  FFFFFFFFH; // extend from most significant bit ELSE

  MASK[i +31:i]  0;

  FI;

  ENDFOR

  MASK[MAXVL-1:128]  0;

  FOR j 0 to 1 k  j * 64; i  j * 32;

  DATA_ADDR  BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP; IF MASK[31+i] THEN

  DEST[i +31:i]  FETCH_32BITS(DATA_ADDR); // a fault exits the instruction

  FI;

  MASK[i +31:i]  0; ENDFOR MASK[127:64]  0;

  DEST[MAXVL-1:64]  0;

  (non-masked elements of the mask register have the content of respective element cleared)

  
  

  
  

  VGATHERDPS (VEX.256 version)

  FOR j 0 to 7 i  j * 32;

  IF MASK[31+i] THEN

  MASK[i +31:i]  FFFFFFFFH; // extend from most significant bit ELSE

  MASK[i +31:i]  0;

  FI;

  ENDFOR

  FOR j 0 to 7 i  j * 32;

  DATA_ADDR  BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP; IF MASK[31+i] THEN

  DEST[i +31:i]  FETCH_32BITS(DATA_ADDR); // a fault exits the instruction

  FI;

  MASK[i +31:i]  0; ENDFOR

  (non-masked elements of the mask register have the content of respective element cleared)

  
  

  VGATHERQPS (VEX.256 version)

  FOR j 0 to 7 i  j * 32;

  IF MASK[31+i] THEN

  MASK[i +31:i]  FFFFFFFFH; // extend from most significant bit ELSE

  MASK[i +31:i]  0;

  FI;

  ENDFOR

  FOR j 0 to 3 k  j * 64; i  j * 32;

  DATA_ADDR  BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP; IF MASK[31+i] THEN

  DEST[i +31:i]  FETCH_32BITS(DATA_ADDR); // a fault exits the instruction

  FI;

  MASK[i +31:i]  0; ENDFOR

  MASK[MAXVL-1:128]  0;

  DEST[MAXVL-1:128]  0;

  (non-masked elements of the mask register have the content of respective element cleared)

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VGATHERDPS: m128 _mm_i32gather_ps (float const * base, m128i index, const int scale);

  VGATHERDPS: m128 _mm_mask_i32gather_ps ( m128 src, float const * base, m128i index, m128 mask, const int scale); VGATHERDPS: m256 _mm256_i32gather_ps (float const * base, m256i index, const int scale);

  VGATHERDPS: m256 _mm256_mask_i32gather_ps ( m256 src, float const * base, m256i index, m256 mask, const int scale);

  VGATHERQPS: m128 _mm_i64gather_ps (float const * base, m128i index, const int scale);

  VGATHERQPS: m128 _mm_mask_i64gather_ps ( m128 src, float const * base, m128i index, m128 mask, const int scale); VGATHERQPS: m128 _mm256_i64gather_ps (float const * base, m256i index, const int scale);

  VGATHERQPS: m128 _mm256_mask_i64gather_ps ( m128 src, float const * base, m256i index, m128 mask, const int scale);

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type 12.

  
  

  VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.128.66.0F38.W0 92 /vsib VGATHERDPS xmm1 {k1}, vm32x	A	V/V	AVX512VL AVX512F	Using signed dword indices, gather single-precision floating- point values from memory using k1 as completion mask.
  EVEX.256.66.0F38.W0 92 /vsib VGATHERDPS ymm1 {k1}, vm32y	A	V/V	AVX512VL AVX512F	Using signed dword indices, gather single-precision floating- point values from memory using k1 as completion mask.
  EVEX.512.66.0F38.W0 92 /vsib VGATHERDPS zmm1 {k1}, vm32z	A	V/V	AVX512F	Using signed dword indices, gather single-precision floating- point values from memory using k1 as completion mask.
  EVEX.128.66.0F38.W1 92 /vsib VGATHERDPD xmm1 {k1}, vm32x	A	V/V	AVX512VL AVX512F	Using signed dword indices, gather float64 vector into float64 vector xmm1 using k1 as completion mask.
  EVEX.256.66.0F38.W1 92 /vsib VGATHERDPD ymm1 {k1}, vm32x	A	V/V	AVX512VL AVX512F	Using signed dword indices, gather float64 vector into float64 vector ymm1 using k1 as completion mask.
  EVEX.512.66.0F38.W1 92 /vsib VGATHERDPD zmm1 {k1}, vm32y	A	V/V	AVX512F	Using signed dword indices, gather float64 vector into float64 vector zmm1 using k1 as completion mask.

  
  

  Instruction Operand Encoding

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Tuple1 Scalar	ModRM:reg (w)	BaseReg (R): VSIB:base, VectorReg(R): VSIB:index	NA	NA

  Description

  A set of single-precision/double-precision faulting-point memory locations pointed by base address BASE_ADDR and index vector V_INDEX with scale SCALE are gathered. The result is written into a vector register. The elements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be loaded if their corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of the destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an exception.

  This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception is triggered by an element other than the right most one with its mask bit set). When this happens, the destination register and the mask register (k1) are partially updated; those elements that have been gathered are placed into the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc- tion breakpoint is not re-triggered when the instruction is continued.

  If the data element size is less than the index element size, the higher part of the destination register and the mask register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may update these unused elements to one or both of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception before gathering any elements.

  Note that:

• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel- 64 memory-ordering model.

• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the conventional order.

• Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to the left of a faulting one may be gathered before the fault is delivered. A given implementation of this instruction is repeatable - given the same input values and architectural state, the same set of elements to the left of the faulting one will be gathered.

  
  

• This instruction does not perform AC checks, and so will never deliver an AC fault.

• Not valid with 16-bit effective addresses. Will deliver a #UD fault.

  Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if ModRM.rm is different than 100b.

  This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.

  The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are ignored.

  The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction will #UD fault if the k0 mask register is specified.

  
  

  Operation

  BASE_ADDR stands for the memory operand base address (a GPR); may not exist VINDEX stands for the memory operand vector of indices (a vector register) SCALE stands for the memory operand scalar (1, 2, 4 or 8)

  DISP is the optional 1, 2 or 4 byte displacement

  
  

  VGATHERDPS (EVEX encoded version)

  (KL, VL) = (4, 128), (8, 256), (16, 512)

  FOR j  0 TO KL-1

  i  j * 32 IF k1[j]

  THEN DEST[i+31:i] 

  MEM[BASE_ADDR +

  SignExtend(VINDEX[i+31:i]) * SCALE + DISP]

  
  

  FI;

  k1[j]  0

  ELSE *DEST[i+31:i]  remains unchanged*

  ENDFOR

  k1[MAX_KL-1:KL]  0

  DEST[MAXVL-1:VL]  0

  
  

  VGATHERDPD (EVEX encoded version)

  (KL, VL) = (2, 128), (4, 256), (8, 512)

  FOR j  0 TO KL-1

  i  j * 64 k  j * 32 IF k1[j]

  THEN DEST[i+63:i]  MEM[BASE_ADDR +

  SignExtend(VINDEX[k+31:k]) * SCALE + DISP]

  
  

  FI;

  k1[j]  0

  ELSE *DEST[i+63:i]  remains unchanged*

  ENDFOR

  k1[MAX_KL-1:KL]  0

  DEST[MAXVL-1:VL]  0

  
  

  
  

  Intel C/C++ Compiler Intrinsic Equivalent

  VGATHERDPD m512d _mm512_i32gather_pd( m256i vdx, void * base, int scale);

  VGATHERDPD m512d _mm512_mask_i32gather_pd( m512d s, mmask8 k, m256i vdx, void * base, int scale); VGATHERDPD m256d _mm256_mmask_i32gather_pd( m256d s, mmask8 k, m128i vdx, void * base, int scale); VGATHERDPD m128d _mm_mmask_i32gather_pd( m128d s, mmask8 k, m128i vdx, void * base, int scale); VGATHERDPS m512 _mm512_i32gather_ps( m512i vdx, void * base, int scale);

  VGATHERDPS m512 _mm512_mask_i32gather_ps( m512 s, mmask16 k, m512i vdx, void * base, int scale); VGATHERDPS m256 _mm256_mmask_i32gather_ps( m256 s, mmask8 k, m256i vdx, void * base, int scale); GATHERDPS m128 _mm_mmask_i32gather_ps( m128 s, mmask8 k, m128i vdx, void * base, int scale);

  
  

  SIMD Floating-Point Exceptions

  None

  
  

  Other Exceptions

  See Exceptions Type E12.

  
  

  VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices

  Opcode/ Instruction	Op/ En	64/32 bit Mode Support	CPUID Feature Flag	Description
  EVEX.128.66.0F38.W0 93 /vsib VGATHERQPS xmm1 {k1}, vm64x	A	V/V	AVX512VL AVX512F	Using signed qword indices, gather single-precision floating-point values from memory using k1 as completion mask.
  EVEX.256.66.0F38.W0 93 /vsib VGATHERQPS xmm1 {k1}, vm64y	A	V/V	AVX512VL AVX512F	Using signed qword indices, gather single-precision floating-point values from memory using k1 as completion mask.
  EVEX.512.66.0F38.W0 93 /vsib VGATHERQPS ymm1 {k1}, vm64z	A	V/V	AVX512F	Using signed qword indices, gather single-precision floating-point values from memory using k1 as completion mask.
  EVEX.128.66.0F38.W1 93 /vsib VGATHERQPD xmm1 {k1}, vm64x	A	V/V	AVX512VL AVX512F	Using signed qword indices, gather float64 vector into float64 vector xmm1 using k1 as completion mask.
  EVEX.256.66.0F38.W1 93 /vsib VGATHERQPD ymm1 {k1}, vm64y	A	V/V	AVX512VL AVX512F	Using signed qword indices, gather float64 vector into float64 vector ymm1 using k1 as completion mask.
  EVEX.512.66.0F38.W1 93 /vsib VGATHERQPD zmm1 {k1}, vm64z	A	V/V	AVX512F	Using signed qword indices, gather float64 vector into float64 vector zmm1 using k1 as completion mask.

  
  

  Instruction Operand Encoding

  
  

  Op/En	Tuple Type	Operand 1	Operand 2	Operand 3	Operand 4
  A	Tuple1 Scalar	ModRM:reg (w)	BaseReg (R): VSIB:base, VectorReg(R): VSIB:index	NA	NA

  Description

  A set of 8 single-precision/double-precision faulting-point memory locations pointed by base address BASE_ADDR and index vector V_INDEX with scale SCALE are gathered. The result is written into vector a register. The elements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be loaded if their corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of the destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it trig- gers an exception.

  This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination register and the mask register (k1) are partially updated; those elements that have been gathered are placed into the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc- tion breakpoint is not re-triggered when the instruction is continued.

  If the data element size is less than the index element size, the higher part of the destination register and the mask register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may update these unused elements to one or both of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception before gathering any elements.

  Note that:

• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel- 64 memory-ordering model.

• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the conventional order.

  
  

• Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to the left of a faulting one may be gathered before the fault is delivered. A given implementation of this instruction is repeatable - given the same input values and architectural state, the same set of elements to the left of the faulting one will be gathered.

• This instruction does not perform AC checks, and so will never deliver an AC fault.

• Not valid with 16-bit effective addresses. Will deliver a #UD fault.